a system is defined as a group of various components interconnected together to perform a specific task. for example, a digital computer consists of several components such as monitor, cpu (central processing unit), memory, keyboard, mouse, printer, and more. all these components are connected together to accomplish certain tasks. hence, a computer can be termed as a system.

we can broadly classify systems into the following two categories −

analog systems
digital systems

an analog system is a type of system that operates on continuous time signals, while a digital system is one that can work on discrete time signals.

read this chapter to learn the basics of digital systems and their types.

what is a digital system?

a type of electronic system that is designed to store, manipulate, and communicate digitally represented information is termed as a digital system. some common examples of digital systems include smartphone, laptops, smartwatch, tablet, desktop computers, etc.

the working of a digital system is entirely based on digital signals or binary signals. where, a digital signal is a type of signal that is represented as a discrete-elements. it can have two possible states namely high or low. the high state is denoted by the logic 1 and the low state is denoted by the logic 0.

in a digital system, if the state of the signal is logic 1, the system will be on, and if the state of the signal is 0, the system will be off.

characteristics of digital systems

today, digital systems are widely used in almost every aspect of life. this is because of their high reliability and efficiency. the following are some key characteristics of digital systems −

digital systems are relative less complex to implement as they use binary number system having only two digits to represent the state of a system.
in digital systems, the information is represented in the form of a group of 0s and 1s i.e., bits. this is called binary or digital representation of information.
digital systems rely on digital signals having two well-defined discrete states. this makes digital systems more reliable and efficient in terms of processing, storage, and communication of information.
digital systems use logical mathematics and operations to perform computing tasks.
digital systems can be manufactured in the form of integrated circuits (ics) of very small sizes.
digital systems can be easily programmed to perform repeated tasks that reduces human efforts and cost.
digital systems are highly immune to noise and distortions.

types of digital systems

digital systems can be classified based on various parameters. here are some important types of digital systems that we commonly use in practice −

combinational digital systems

a combinational logic circuit or system is a type of digital circuit that performs logical operations and produces output depending on the present inputs. hence, the output of a combinational digital circuit does not depend on the past inputs and outputs of the system.

example − the common examples of combinational digital systems are binary adders, subtractors, logic gates, multiplexers, demultiplexers, etc.

sequential digital systems

a type of digital system that has a memory element to store past history of the system operation is called a sequential digital system. therefore, the output of a digital system depends on both present inputs and past outputs of the system.

example of sequential digital systems are flip-flops, registers, memory devices, counters, etc.

programmable logic devices (plds)

a programmable logic device is one that can be programmed to perform a specific task automatically.

example of programmable logic devices are microcontrollers, plcs, etc.

digital communication systems

a digital communication system is a type of digital system used for transmission and reception of information in the form of digital signals.

example of digital communication systems are internet, intranet, mobile communication system, wi-fi, etc.

digital control systems

a digital control system is a computerized control system used to monitor and regulate the behavior of a dynamic system.

example − digital control systems are extensively used in robotics, industrial automation, etc.

conclusion

in conclusion, digital systems are modern systems known for their high speed and reliability. a digital system utilizes digital signals to store, process, and communicate the information.

in this chapter, we explained the basics of digital systems and their types. traverse to the next chapter to learn all about the types of signals used in the field of electronics engineering.

in electronics engineering, an electrical quantity like voltage or current or electromagnetic wave that is used for transmission of data or information is called a signal.

signals are considered the heart of any data communication or processing system like the internet. signals instruct the electronics hardware components to perform a certain task such as convey the information from one point to another.

apart from voltage, current or electromagnetic signals, we also have optical signals, where the information is represented and transmitted in the form of light.

this chapter will explain the concept of signal and different types of signals used in electronics engineering.

what is a signal?

a physical quantity that has capability to transmit information from one point to another is called a signal. some common examples of signals include voltage, current, electromagnetic wave, optical signals, etc.

signals are the backbone of any electronic processing or communication system. these can be transmitted through various types of communication channels like wires, space (electromagnetic waves), optical fibers, etc.

properties of signal

in electronics, a signal is characterized by the following important properties −

magnitude − the intensity or maximum value of a signal is termed as its magnitude.
frequency − the number of oscillations per second is called frequency of the signal.
time period − the time taken to complete one oscillation is called the time period of the signal.

types of signals

in electronics, there are mainly two types of signals used, they are −

analog signals
digital signals

let us discuss these two types of signals in detail.

what is an analog signal?

a type of electronic signal that has continuous values within a given range is called an analog signal. analog signals are expressed as the continuous functions of time. they are represented as the waveforms of continuously varying current or voltage.

example of analog signals are voice, speed, pressure, temperature, etc.

an important characteristic of analog signals is that they have a definite value at every instant of time, known as instantaneous value of the signal.

analog signals have smooth waveforms as they are continuous in both amplitude and time. that meant, there is no interruptions in their representation over time.

properties of analog signal

the following are main properties of analog signals −

analog signals are continuous signals in both amplitude and time.
analog signals have a certain value or magnitude at any given instant of time.
analog signals have infinite resolution.
analog signals are best suited for representing the real-world phenomena.
analog signals are represented by the continuously varying smooth waveforms.

what is a digital signal?

a digital signal is a type of electronic signal that has a finite set of discrete values representing information.

digital signals are also called binary signals, as they use binary 0 or 1 to represent the state of a signal. where, the binary 0 represents the off or low state of the signal, while the binary 1 represents the on or high state of the signal.

thus, digital signals are expressed as discontinuous functions of time.

properties of digital signal

the following are some key characteristics of digital signals −

digital signals have discrete or discontinuous values in terms of both amplitude and time.
digital signals do not have values defined between any two distinct instants of time.
digital signals are represented using binary system by sampling the values of the signals at specific time instants.
digital signals represent information in the form of a sequence of binary 0s and 1s.
digital signals have a finite resolution.
digital signals are capable to perform logical operations.
digital signals are more efficient and reliable when it comes to storage and transmission.

difference between analog and digital signals

let us now discuss the important differences between analog and digital signals −

key	analog signals	digital signals
representation	analog signals are represented as continuous functions or waveforms of time.	digital signals are represented as discrete functions of time.
nature	analog signals are continuous as they have infinite values within a specified range.	digital signals are discontinuous as they have distinct values sampled at specific time instants.
resolution	analog signals have infinite resolution.	digital signals have a finite resolution.
accuracy	analog signals are more accurate.	digital signals are relatively less accurate.
storage	analog signals are difficult to store.	digital signals are efficient to store.
noise immunity	analog signals are less immune to noise.	digital signals have high immunity against noise.
examples	voice signals, temperature, speed, etc.	data transmitted over internet, computer generated signals, etc.

applications of signals

both analog and digital signals are widely used in the field of electronics. the following are some key applications of signals −

signals are used for storage and transmission of information.
signals are used in control systems to regulate their behavior.
signals are also used in measurement of physical quantities like temperature, pressure, speed, sound, light, and more.
signals are used in computing systems for data processing, etc.

conclusion

in electronics engineering, signals are most significant elements of a system. signals are nothing but physical quantities like voltage, current, electromagnetic waves, light pulses, etc. used to convey information from one point to another.

in this chapter, we covered different types of signals and their properties. in the next chapter, we will cover the concept of logic levels and pulse waveform.

a digital system is a type of electronic system that utilizes the binary number system to work. in other words, a digital system is a two-state electronic system used to represent two binary digits 0 and 1, where 0 represents the low or "off" state and 1 represents the high or "on" state of the system.

in the field of digital electronics, different voltage levels are used to represent the two binary values, i.e., 0 and 1 in a digital signal. these voltage levels are known as logic levels.

in this chapter, we will learn the concept of logic levels and pulse waveforms.

what is a logic level?

in digital electronics, a voltage level that represents a specific binary value either 0 or 1 is called a logic level. here, the binary value 0 represents the low voltage level while the binary value 1 represents the high value level.

hence, the logic levels can be classified into the following two types −

high logic level
low logic level

lets discuss these two logic levels in detail.

high logic level

in the case of a digital system, the voltage level closer to the maximum voltage level that the system can handle without getting damaged is called high logic level.

the high logic level is represented by the binary digit "1". the voltage level for a high logic level depends on the technological standard used to design the system. typically, the voltage value between 2 v and 5 v represents the high logic level or 1.

low logic level

in a digital system, the low logic level is defined as the maximum voltage level for which the system will remain in the off state.

the low logic level is represented by the binary digit "0". similar to the high logic level, the voltage level for a low logic level depends on the technology standard used to design the system. in actual practice, the voltage value between 0 v and 0.8 v represents the low logic level or logic 0.

in most practical digital system, the ground voltage is used to represent the low logic level.

note − the voltage range between the voltage values 0.8 v and 2 v is known as the indeterminate logic range. if a digital signal lies between the value 0.8 and 2 v, the response of the system is not predictable.

what is a pulse?

a pulse is a type of an electronic signal that can change suddenly between two possible states i.e., high state and low state.

the graph used to represent the transition of a pulse is called the pulse waveform. pulses are very important in the operation of digital systems, communication systems, and many other electronics devices and circuits.

depending on the switching characteristics, the pulses can be classified into the following two types −

positive pulse − when a signal normally goes from low logic level to the high logic level and then returns to its normal low logic level, then it is called a positive pulse.
negative pulse − when a signal normally goes from high logic level to the low logic level and then returns to its normal high logic level, then it is known as a negative pulse.

the pulse waveforms for positive and negative pulses are depicted in the following figure.

a pulse has two edges namely, a leading edge and a trailing edge.

in the case of a positive pulse, the edge going from low logic level to high logic level is called the leading edge, and the edge going from high logic level to low logic level is called the trailing edge.

in the case of a negative pulse, the edge going from high logic level to low logic level is called the leading edge, whereas the edge going from low logic level to high logic level is called the trailing edge.

the positive and negative pulse waveforms shown in the above figure are ideal pulse waveforms, because their leading and trailing edges change instantaneously i.e., in zero time. but in actual practice, the edges of pulses do not change instantaneously from low logic level to high logic level or from high logic level to low logic level.

the pulse waveforms that take a finite time to change from low logic level to high logic level and vice-versa are known as non-ideal pulse waveforms.

in the case of a non-ideal pulse waveform, the time taken by the pulse to go from low logic level to high logic level is called the rise time. the time taken by the pulse to go from the high logic level to the low logic level is called the fall time.

types of pulse waveforms

the pulse waveforms used in digital systems are mainly classified into the following two types −

periodic waveforms

a pulse waveform that repeats itself at regular intervals of time is called a periodic waveform. the time taken to complete one cycle is called the time period of the periodic waveform.

non-periodic waveforms

a pulse waveform which does not repeat itself at regular intervals of time is termed as a non-periodic or aperiodic waveform.

conclusion

in conclusion, "logic level" is a concept used in digital systems to represent the state of the system. there are two possible logic levels in the case of digital systems namely, high logic level and low logic level. the high logic level is represented by the binary 1 while the low logic level is represented by the binary 0.

the graphical representation of a digital signal or a pulse is termed as the "pulse waveform". pulse waveforms are used to represent the transition of a pulse or digital signal or the states of a digital system. in this chapter, we have discussed the concept of logic levels and pulse waveforms. in the next chapter, we will learn about "components of a digital system".

a digital system is a type of electronic system used to store, process, and manipulate data represented in the form of digital signals, where a digital signal is a discrete time signal. digital systems use binary number system to operate. some common examples of digital systems include digital computers, laptops, smartphones, etc.

this chapter is meant for explaining the major components of a digital system.

components of a digital system

a typical digital system consists of the following main components −

central processing unit (cpu)
memory
input devices
output devices
logic gates
power supply
communication channels

lets discuss each of these components of a digital system in detail.

central processing unit (cpu)

in a digital system, the central processing unit is the most important component of the system, as it performs all the operations in the system. it is also known as processor.

the cpu is an electronic circuit that consists of two sub-circuits namely, arithmetic and logic unit, and control unit.

the arithmetic logic unit (alu) is the part of a cpu that performs all the arithmetic and logical operations and executes the instructions to manipulate data. alu is made up of logic gates and other electronic components. it can perform operations like addition, subtractions, comparison, etc.

the control unit (cu) is another major electronic circuit in the central processing unit that coordinate the operation of all other components of a digital system. it generates clock signals for the synchronization of the system.

semiconductor memory

memory is another major component of a digital system. it is used to store and instructions in the system. in most digital system, semiconductor memory is used to store digital information.

memory of a digital system can be classified into the following two types −

random access memory (ram) − it is a temporary memory used to store data and instruction on which the cpu is currently working. once the digital system is turned off, its data will be deleted.
read only memory (rom) − rom is also an important component of a digital system. it is a permanent memory used to store those data and instructions that require again and again to perform tasks.

in digital systems, both ram and rom are used in the form of ics made up of semiconductors.

apart from ram and rom, digital systems may also support external memory devices like cd, dvd, pen drive, sd card, etc. all these external memories are used for permanent data storage.

input devices

input devices are those electronic components of a digital system used for entering data into the system. examples of input devices include keyboard, mouse, scanner, sensors, camera, light pen, code readers, etc.

input devices are designed to accept data in the form of a specific type or format and convert them into digital signals for processing.

for example, a keyboard gets outside instructions in the form of keystrokes and then convert them into digital signals.

output devices

output devices are those components of a digital system that allow users to view the processed data or information. examples of output devices are monitor, display screens, printers, projectors, speakers, etc.

output devices are designed to accept digital signals and convert them in a suitable format to make them readable by human.

for example, a monitor takes digital signals and convert them as visuals and display on a screen.

logic gates

logic gates are essential components of any digital system. they are the fundamental building block of the digital system. logic gates are nothing but electronic circuits that can perform logical operations.

in digital systems, logic gates are used to realize all the information processing and storage systems. the most commonly used logic gates are and, or, not, nand, nor, ex-or, and ex-nor.

power supply

power supply is the energy bank of the digital system that provides necessary electric power to the components of the system so they can work.

the primary function of the power supply unit of a digital system is to convert the electric power received from an external source into the desired type and voltage level required by the system.

most digital systems work on 5 v dc supply. hence, the power supply unit receives 220 v ac from the supply mains and convert it to 5 v dc supply. also, the power supply unit regulates the fluctuations occurring in the power supply to protect the system from damages.

communication channels

in a digital system, the communication channel is also known as bus system. it consists of several different types of buses (conductors) such as data bus, address bus, and control bus. these communication channels allow data transmission between different components of the system.

conclusion

in conclusion, a digital system consists of several components. some important components of a typical digital system are described in this chapter. all these components are connected together and allowed to communicate to perform different jobs. in the next chapter, we will learn about different types of "digital logic operations".

in the field of digital electronics, many digital logic operations are performed which are considered as the fundamental building blocks. all the digital logic operations are based on the binary number system and boolean algebra, where the data and information are represented in the form of binary 0s and 1s. digital logic operations are used to manipulate the binary digits to perform various tasks.

in this chapter, we will learn about commonly used digital logic operations in the field of digital electronics. here are some widely used digital logic operations −

arithmetic operations
logical operations
encoding and decoding
multiplexing and demultiplexing
code conversion
comparison
counting
data storage
data transmission

lets discuss each of these digital logic operations in detail along with their applications.

arithmetic operations in digital electronics

arithmetic operations are basic mathematical operations like addition, subtraction, multiplication, division, etc. in digital electronics, these arithmetic operations are performed using various digital circuits like adders, subtractors, multiplier, etc.

in digital electronic systems, the given numbers are first converted into binary format and then desired operations are performed on them.

arithmetic operations are one of the fundamental operations performed using various digital electronic systems like microprocessors, calculators, microcontrollers, etc.

the following are the four main arithmetic operations performed by a digital system −

addition

addition is performed by using a digital logic circuit called adder. it adds two numbers and generates a sum and a carry as output. for example, if 8 and 5 are two numbers, then adder will produce a sum term 3 and a carry output 1.

subtraction

the arithmetic operation subtraction is performed by using a digital logic circuit called subtractor. it performs the subtraction of two numbers and produces a difference term and a borrow term as output.

multiplication

a digital circuit used to perform multiplication of two numbers is called a multiplier. it multiplies the given numbers and generates a product term as output.

division

the division operation of two numbers is performed by using a digital circuit called divider. it performs division of two numbers and generates a quotient term and remainder term as output.

logical operations in digital electronics

logical operations are used to compare two input parameters to make a decision. the commonly used logical operations in digital systems are or, and, not, nand, nor, xor, and xnor. all these logical operations are used to manipulate binary data to make crucial decisions in a digital system.

logical operations are widely used for developing algorithms and conditional statements in programming.

here are the commonly used logical operations in digital electronics −

and

it is a basic logic operation performed by using a digital circuit called and gate. in the and operation, the output is true only if all of the inputs are true.

or

or is another basic logic operation in digital electronics. it is performed by using a digital logic circuit called or gate. it produces a true output if any of the inputs are true.

not

not is a digital logic operation performed by using a circuit called not gate or inverter. it is also known as inversion operation. it generates a complement of the input.

nand

nand is a combination of and and not operation. it is performed by using a digital circuit called nand gate. the output of the nand gate is false only if all of the inputs are true.

nor

this logical operation is a combination of or and not operations. it is performed by using a digital circuit called nor gate. in the case of nor operation, the output is false if any of the inputs are true.

xor

the logical operation xor or exclusive or is performed by using a digital logic circuit called xor gate. in the case of xor operation, the output is true if the number of true inputs is odd.

xnor

the logical operation xnor is a combination of xor and not operations. it is performed by using a digital logic circuit called xnor gate. in the case of xnor gate, the output is true if all of the inputs are either true or false.

encoding and decoding in digital electronics

in digital electronics, encoding is a digital logic operation used to convert a familiar number or symbol into a coded format. a digital circuit called encoder is used to perform encoding, where the encoder receives digits, alphabets, and symbols and converts them into their respective binary codes.

on the other hand, decoding is the inverse operation of encoding. it is performed by using a digital logic circuit called decoder. decoding is a digital logic operation that involves the conversion of a binary-coded information to other format like decimal, octal, hexadecimal, alphabets or symbols.

both encoding and decoding are used in digital communication, error correction, data compression, etc.

multiplexing and demultiplexing in digital electronics

multiplexing is a digital logic operation that combines multiple signals into a single signal. hence, it is also termed as data sharing or selecting. a digital circuit called multiplexer is used to perform multiplexing. multiplexing involves the process of switching information from multiple input lines on to a single output line in a specific sequence.

demultiplexing is the reverse process of multiplexing. in the case of demultiplexing, information is switched from one input line on to multiple output lines. the digital circuit used to perform demultiplexing is called a demultiplexer.

multiplexing and demultiplexing are two widely used digital logic operation in optimization of communication channels.

code conversion in digital electronics

code conversion is a digital logic operation that involves converting information coded in one form to another form. it is performed by using a digital circuit called code converter.

code conversion is an essential operation in interfacing between different digital systems. some common examples of code converters are bcd to xs-3 converter, xs-3 to gray converter, etc.

comparison operation in digital electronics

comparison is a digital logic operation performed using a digital circuit called comparator. the comparator compares two quantities and generates an output signal indicating whether the two input quantities are equal or not.

counting operation in digital electronics

counting is a digital logic operation performed by using a digital circuit called counter. it involves the counting of increase or decrease in binary numbers.

counting operation plays a vital role in various digital devices like memory, timers, digital clocks, microprocessors, etc. it is used to control the sequence of operation in a digital system.

data storage in digital electronics

data storage is an essential operation in digital systems. it involves storing and retrieving digital data and information stored in the memory devices. data storage can be performed using various digital storage devices like flip-flops, registers, memory units, etc.

data transmission in digital electronics

data transmission is a digital logic operation in which binary data is transferred from one point to another in a digital system. in digital electronics, data transmission can be done either through wires or wireless channels.

data transmission is a fundamental operation in digital communication where data is exchanged between different components of the system.

conclusion

in conclusion, digital logic operations are used to manipulate binary data to perform various operations. they are considered as the fundamental building blocks of digital systems like microprocessors, microcontrollers, memory devices, communication systems, etc. hence, it is essential to understand the digital logic operations for designing reliable digital systems and understand their behavior.

in this chapter, we covered all the essential digital logic operations along with their applications. in the next chapter, we will learn the advantages and limitations of digital systems.

a digital system is an interconnected group of components that can process, store, and transmit digital data i.e., data represented in the form of binary codes. digital signals are represented using binary values, 0s and 1s. a digital system can understand and manipulate data and information represented in the form of 0s and 1s.

digital systems are implemented using highly reliable and efficient electronics components like logic gates and integrated circuits (ics). they are known for their high speed and reliability.

digital systems are extensively used in various fields like communication, computing, control system, data processing, etc.

examples of digital systems are computers, smartphones, tablets, telecommunication networks, etc. today, digital systems form an essential part of our modern technological world. in this chapter, let's focus on the advantages and disadvantages of digital systems.

advantages of digital systems

digital systems offer several advantages over analog systems. some of the important advantages of digital systems are explained below −

easy to design

as we know, digital systems are two state switching circuits that have only two voltage levels namely, high and low. hence, it is easier to design a digital system.

in the case of digital systems, the knowledge of intermediate values of voltages are not important, but the lower and upper limits in which they fall are important. therefore, digital circuits are less complex to design and implement.

easy information storage

in digital systems, data and information are represented in the form of binary digits, i.e., 0s and 1s. there are several types of magnetic, optical, and semiconductor memories available to store digital data.

it is very easy to store digital information in a digital storage device like pen drive that provides a compact and efficient method to store data for long periods as compared to analog storage devices.

high accuracy and precision

digital systems have higher accuracy and precision as compared to analog systems. this is because, it is very easy to expand a digital system to handle more binary digits just by adding more digital circuits to the system.

also, digital systems are highly immune to interference. hence, they can process, store, and transmit data without loss of accuracy.

flexibility in programming and versatility

the operation of a digital system can be controlled by writing a set of instructions called program. we can easily reprogram the system to change its operation without changing its hardware configuration. hence, digital systems are more versatile than analog systems.

high noise immunity

in digital electronics, unwanted electronic signals are called noise. the electronic noise can disturb the normal operation of a system. digital systems can have various error checking and correction mechanisms that make them more immune to noise and interference over analog systems.

high reliability and durability

digital systems use components that are less susceptible to variations and aging. this characteristic makes the digital systems more reliable and durable as compared to analog systems. hence, digital systems can be used with consistent performance for long periods.

easy fabrication on ic chips

the fabrication of digital integrated circuits is simple and less costly as compared to analog ics. also, higher degree of integration can be achieved in the case of digital ics, as the digital ics do not require high value capacitors, precision resistors, and inductors.

high security

digital systems are highly secure than analog systems, as we can implement various advanced security and encryption technologies to protect sensitive information stored in the system.

all these are the major benefits of digital systems that make them suitable for various applications like computing, telecommunication, automation, robotics, and more.

however, digital systems also have certain limitations over analog systems. lets discuss these limitations of digital systems in the following section.

limitations of digital systems

digital systems have numerous advantages, but they can also have some limitations that play a vital role in their designing and applications. the following are some key limitations of digital systems −

need of analog to digital conversion

in the real world, most physical quantities are analog in nature. hence, before processing using a digital system, we need to convert these analog quantities into digital form. at the end of processing, the results are also converted back to the analog form.

increased complexity and cost

as the digital systems require analog to digital and digital to analog converter and complex algorithms to perform operations. these practices increase complexity and cost of designing of the system.

slow processing speed

although digital systems have fast speeds, they cannot be used in some real-time applications due to need of extremely high processing speed. under such situations, analog systems are more suitable over digital systems.

sampling rate limitations

real-world signals are analog, hence, proper sampling is important while converting them into digital signals. if the sampling rate is not chosen correctly, it can result in the loss of information in the digital system. hence, digital systems are also subjected to a limitation in sampling rate.

voltage level limitations

as digital systems use binary volage levels i.e., high and low voltages. therefore, they are limited in a certain range of voltage levels. due to this reason, digital systems cannot be used in applications where a continuous range of voltages is required.

conclusion

digital systems have several advantages that make them suitable to use in modern technological applications. due to high reliability, ease of integration, high security, etc. digital systems are being widely used in various fields like telecommunication, medical, science, research, etc.

electronics engineers and designers are continuously working to optimize the digital systems to increase their performance and area of applications.

digital systems however have some limitations like finite resolution, limited voltage levels and sampling rates, relatively slow speed, etc. these limitations have to be addressed while designing and implementation for better advancement in digital technologies.

a digital number system is a positional number system that has some symbols called digits. it provides a complete set of digits, operators, and rules to perform operations.

in a digital number system, the number of digits used determines the base of the number system. for example, the binary number system has two digits (0 and 1), hence, the base of the binary number system is 2.

digital number systems form the foundation of the modern computing technologies and digital electronics. they are used to represent, process, and manipulate the information using a digital system.

in this chapter, we will discuss the fundamental concepts of different types of digital number systems.

types of digital number systems

in digital electronics, the following four types of digital number systems are mainly used −

binary number system
decimal number system
octal number system
hexadecimal number system

lets discuss each of these number systems in detail.

binary number system

binary number system is the fundamental building block behind the implementation and working of all digital systems.

binary number system has two symbols or digits, i.e., 0 and 1. hence, these two digits are used to represent information and perform all the digital operations. each binary digit is called a bit.

since there are two digits are used in the binary number system, hence its base is 2. therefore, the value of a binary number is calculated as the sum of powers of 2.

binary digits are used in digital system to represent their on and off states. where, 0 is used to represent the off state of the digital system and 1 is used to represent the on state of the system.

overall, the binary number system forms the foundation of computation, digital communication, and digital information storage.

example

consider the binary number 1101.011. the integer part of this number is 1101 and the fractional part of this number is 0.011. the digits 1, 0, 1 and 1 of the integer part have weights of 2⁰, 2¹, 2², 2³ respectively. similarly, the digits 0, 1 and 1 of fractional part have weights of 2^-1, 2^-2, 2^-3 respectively.

mathematically, we can write it as,

$$\mathrm{1101.011 \: = \: (1 \: \times \: 2^{3}) \: + \:(1 \: \times \: 2^{2}) \: + \: (0 \: \times \: 2^{1}) \: + \: (1 \: \times \: 2^{0}) \: + \: (0 \: \times \: 2^{−1}) \: + \: (1 \: \times \: 2^{−2}) \: + \: (1 \: \times \: 2^{−3})}$$

after simplifying the right-hand side terms, we will get a decimal number, which is an equivalent of binary number on left-hand side.

decimal number system

decimal number system is not inherently a digital number system. but it is widely used to represent the digital information in a human readable format.

decimal number system is a base 10 number system having 10 unique digits i.e., 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9. it is the standard number system used by human beings to represent information in a natural way. however, a digital system cannot directly process the information represented in decimal form, so it is converted into binary form and then processed.

the base of the decimal number system is 10. so, the value of a decimal number is calculated by the sum of powers of 10.

example

consider the decimal number 1358.246. the integer part of this number is 1358 and the fractional part of this number is 0.246. the digits 8, 5, 3 and 1 have weights of (10)⁰, (10)¹, (10)² and (10)³ respectively. similarly, the digits 2, 4 and 6 have weights of (10)^-1, (10)^-2 and (10)^-3 respectively.

mathematically, we can write it as,

$$\mathrm{1358.246 \: = \: (1 \: \times \: 10^{3}) \: + \:(3 \: \times \: 10^{2}) \: + \: (5 \: \times \: 10^{1}) \: + \: (8 \: \times \: 10^{0}) \: + \: (2 \: \times \: 10^{−1}) \: + \: (4 \: \times \: 10^{−2}) \: + \: (6 \: \times \: 10^{−3})}$$

after simplifying the right-hand side terms, we will get the decimal number, which is on the left-hand side.

octal number system

the octal number system is another type of digital number system used in the field of digital electronics to represent information. it is a base 8 number system having eight unique digits i.e., 0, 1, 2, 3, 4, 5, 6, and 7.

it is important note that the octal number system is equivalent to 3-bit binary number system as 2³ = 8. hence, this number system can be used in computing and digital electronic applications.

the value of an octal number is obtained by the sum of powers of 8, as 8 is the base of the octal number system.

octal number system is used in the field of digital electronics to represent binary information in compact form, permissions in linux or unix systems, ipv6 address, binary machine code instructions, in error detection algorithms, etc.

example

consider the octal number 1457.236. integer part of this number is 1457 and fractional part of this number is 0.236. the digits 7, 5, 4 and 1 have weights of (8)⁰, (8)¹, (8)² and (8)³ respectively. similarly, the digits 2, 3 and 6 have weights of (8)^-1, (8)^-2, (8)^-3 respectively.

mathematically, we can write it as,

$$\mathrm{1457.236 \: = \: (1 \: \times \: 8^{3}) \: + \:(4 \: \times \: 8^{2}) \: + \: (5 \: \times \: 8^{1}) \: + \: (7 \: \times \: 8^{0}) \: + \: (2 \: \times \: 8^{−1}) \: + \: (3 \: \times \: 8^{−2}) \: + \: (6 \: \times \: 8^{−3})}$$

after simplifying the right-hand side terms, we will get a decimal number, which is an equivalent of octal number on the left-hand side.

hexadecimal number system

the hexadecimal number system is a base 16 number system. it has 16 digits, 0 to 9 and a to f. where, a represents 10, b represents 11, c represents 12, d represents 13, e represents 14, and f represents 15. the hexadecimal number system is equivalent to a 4-bit binary number system as 2⁴ = 16. thus, the value of a hexadecimal number can be calculated by the sum of powers of 16.

in the field of digital electronics, the hexadecimal number system is used in memory address representation, digital colors representation, low level computer programming, encoding, assembly language programming, microcontrollers, keyboards, etc. hexadecimal number system creates a balance between digital representation and human readability.

example

consider the hexadecimal number 1a05.2c4. the integer part of this number is 1a05 and the fractional part of this number is 0.2c4. the digits 5, 0, a and 1 have weights of (16)⁰, (16)¹, (16)² and (16)³ respectively. similarly, the digits 2, c and 4 have weights of (16)^-1 , (16)^-2 and (16)^-3 respectively.

mathematically, we can write it as,

$$\mathrm{1a05.2c4 \: = \: (1 \: \times \: 16^{3}) \: + \:(10 \: \times \: 16^{2}) \: + \: (0 \: \times \: 16^{1}) \: + \: (5 \: \times \: 16^{0}) \: + \: (2 \: \times \: 16^{−1}) \: + \: (12 \: \times \: 16^{−2}) \: + \: (4 \: \times \: 16^{−3})}$$

after simplifying the right-hand side terms, we will get a decimal number, which is an equivalent of the hexadecimal number on the left-hand side.

advantages of digital number systems

the following are some key advantages of digital number systems −

digital number systems provide a simple and consistent way of representing and understanding information.
digital number systems allow to develop efficient methods for storage and transmission of digital information.
digital number systems provide methods of representing different types of information like text, numbers, images, etc.
digital number systems allow to convert information from one form to full fill the needs of applications.
digital number systems create compatibility between hardware and software.

applications of digital number systems

digital number systems are used in various digital electronic fields such as computing, internet, communication, signal processing, and more. here are a few examples of applications of digital number systems −

information representation
digital communication
storage and transmission of digital data and information
algorithm development
system programming, etc.

conclusion

in this chapter, we discussed the basic concepts of digital number systems. the understanding of digital number systems is essential for designing, implementing, and troubleshooting the digital systems. digital number systems provide different methods of representing and manipulating information in digital systems.

in the previous chapter, we explained the different types of number systems used in digital electronics. in this chapter, we will explain how you can convert a number from one base to another.

what is number system conversion?

number system conversion is a process of converting a number from one base to another. number system conversion is an important concept to represent information in different forms. in digital electronics, the following number system conversions are mostly performed.

binary to decimal conversion
decimal to binary conversion
binary to octal conversion
octal to binary conversion
octal to decimal conversion
decimal to octal conversion
hexadecimal to binary conversion
binary to hexadecimal conversion
hexadecimal to decimal conversion
decimal to hexadecimal conversion
octal to hexadecimal conversion
hexadecimal to octal conversion

let us understand each of these number system conversions with the help of examples.

binary to decimal conversion

we can convert a binary number into its equivalent decimal number by using the positional weights method.

in this method of binary to decimal conversion, each digit of the given binary number is multiplied by its positional weight. then, all the products are added to obtain the equivalent decimal number.

the step-by-step process of converting a binary number to its equivalent decimal number by using positional weights method is explained below −

step 1 − write the positional weights for each binary digit.

step 2 − multiply each binary digit with its positional weight.

step 3 − add the product terms to obtain the equivalent decimal number.

let us consider some examples to understand the binary to decimal conversion.

example 1

convert (101101)₂ into decimal equivalent.

solution

the given binary number is (101101)₂

step 1 − defining positional weights for the given binary number −

bits	1	0	1	1	0	1
weights	2⁵	2⁴	2³	2²	2¹	2⁰

step 2 − calculating product of bits and positional weights −

bits	weights	multiply	product
1	2⁵	1 × 32	32
0	2⁴	0 × 16	0
1	2³	1 × 8	8
1	2²	1 × 4	4
0	2¹	0 × 2	0
1	2⁰	1 × 1	1

step 3 − add all the product terms to obtain the equivalent decimal number −

decimal number = 32 + 0 + 8 + 4 + 0 + 1 = (45)₁₀

hence, the decimal equivalent of (101101)₂ is (45)₁₀.

example 2

convert (1111011)₂ into decimal equivalent.

solution

multiplying bits with positional weights, we get,

decimal number = 1 × 2⁶ + 1 × 2⁵ + 1 × 2⁴ + 1 × 2³ + 0 × 2² + 1 × 2¹ + 1 × 2⁰

decimal number = 64 + 32 + 16 + 8 + 0 + 2 + 1 = (123)₁₀

hence, the decimal equivalent of (1111011)₂ is (123)₁₀.

example 3

convert (1001.11)₂ into decimal.

solution

the given binary number has integer and fractional parts. the integer part is multiplied with positive weights, while the fractional part is multiplied with negative weights as follows −

decimal number = 1 × 2³ + 0 × 2² + 0 × 2¹ + 1 × 2⁰ + 1 × 2^-1 + 1 × 2^-2

decimal number = 8 + 0 + 0 + 1 + 0.5 + 0.25 = (9.75)₁₀

thus, the decimal equivalent of (1001.11)₂ is (9.75)₁₀.

decimal to binary conversion

a decimal number can be converted to their equivalent binary number by using the double-dabble method. in this method, the integer part of the given decimal number is successively divided by 2 and the fractional part is successively multiplied by 2.

in the integer part, the remainders read from bottom to top give the integer part of the binary equivalent. in the fractional part, the carries read from top to bottom give the fractional part of the binary equivalent.

the following steps are followed to convert a decimal number to the binary equivalent −

step 1 − divide the integer part of the given decimal number successively by 2 and read the remainders from bottom to top.

step 2 − multiply the fractional part of the given decimal number successively by 2 and read the carries from top to bottom.

let us see some examples to understand the conversion of a decimal number into its equivalent binary number.

example 1

convert (28)₁₀ to binary equivalent.

solution

the given decimal number is an integer. thus, we divide the decimal number successively by 2 and read the remainders upwards to obtain the equivalent binary number.

	decimal	remainders
2	28
2	14	0
2	7	0
2	3	1
2	1	1
	0	1

reading the remainders from bottom to top, the result will be (11100)₂. it is the binary equivalent of (28)₁₀.

example 2

convert (165.75)₁₀ to its equivalent binary.

solution

the given decimal number is a mixed number having both integer and fractional parts. thus, to obtain its equivalent binary number, we convert the integer and fractional parts separately.

the binary equivalent of 165₁₀ is obtained as follows,

	decimal	remainders
2	165
2	82	1
2	41	0
2	20	1
2	10	0
2	5	0
2	2	1
2	1	0
	0	1

reading the remainders from bottom to top, the binary equivalent of 165₁₀ is (10100101)₂.

now, let's convert the fractional part (0.75) of the given number.

to convert the given decimal fraction into binary, we multiply it by 2, as follows,

decimal	product	carry
0.75 × 2	1.5	1
0.5 × 2	1.0	1
0 × 2	0

reading the carries from top to bottom, the result is 0.11. thus, the binary equivalent of (0.75)₁₀ is (0.11)₂.

therefore, (165.75)₁₀ = (10100101.11)₂

binary to octal conversion

a binary number can be converted into its equivalent octal number by mapping method. the conversion of a binary number to the octal equivalent is done as per the following steps −

step 1 − starting from the binary point, make groups of 3-bits on both sides of the binary point.

step 2 − replace each group of 3-bit binary by the equivalent octal digit.

the following table shows the equivalent octal digital for each 3-bit binary group −

octal	binary
	(2)² = 4	(2)¹ = 2	(2)⁰ = 1
0	0	0	0
1	0	0	1
2	0	1	0
3	0	1	1
4	1	0	0
5	1	0	1
6	1	1	0
7	1	1	1

let us understand the binary to octal conversion with the help of examples.

example 1

convert (110011101.110101)₂ to its octal equivalent.

solution

the binary to octal conversion will be performed as follows −

3-bit group	110	011	101	.	110	101
octal equivalent	6	3	5	.	6	5

hence, the octal equivalent of given binary number is (635.65)₈.

example 2

convert (1110111011.11101)₂ to octal equivalent.

solution

the conversion of given binary number to octal number is given below −

3-bit group	1	110	111	011	.	111	01
	011	110	111	011	.	111	010
octal equivalent	3	6	7	3	.	7	2

hence, the octal equivalent of (1110111011.11101)₂ is (3673.72)₈.

octal to binary conversion

we can also use the mapping method to convert an octal number into its equivalent binary number. in this method, we just replace each digital of the given octal number by its 3-bit binary equivalent.

lets understand the conversion of octal number to binary equivalent with the help of examples.

example 1

convert (3572.126)₈ to binary equivalent.

solution

the given octal number is converted into binary equivalent as follows −

octal number	3	5	7	2	.	1	2	6
3-bit binary equivalent	011	101	111	010	.	001	010	110

hence, the binary equivalent of (3572.126)₈ is (011101111010.001010110)₂.

example 2

convert (364.52)₈ to its binary equivalent.

solution

the conversion of given octal number to its equivalent binary number is given below −

octal number	3	6	4	.	5	2
3-bit binary equivalent	011	110	100	.	101	010

thus, the binary equivalent of the octal number (364.52)₈ is (011110100.101010)₂.

octal to decimal conversion

the conversion of an octal number to its equivalent decimal number is same as the binary to decimal conversion. to convert an octal number to its decimal equivalent, we multiply each digit of the octal number by its positional weight and then add all the product terms to obtain the equivalent decimal number.

the step-by-step procedure to convert an octal number to its equivalent decimal number is given below −

step 1 − write the positional weights for each octal digit.

step 2 − multiply each octal digit with its positional weight.

step 3 − add the product terms to obtain the equivalent decimal number.

let us understand the conversion of octal number to decimal number with the help of examples.

example 1

convert (356.25)₈ to its decimal equivalent.

solution

the given octal number can be converted to equivalent decimal number as follows −

octal digits	positional weights	multiply	product
3	(8)²	3 × (8)²	192
5	(8)¹	5 × (8)¹	40
6	(8)⁰	6 × (8)⁰	6
.	.	.	.
2	(8)^-1	2 × (8)^-1	0.25
5	(8)^-2	5 × (8)^-2	0.078

adding all the product terms to obtain the equivalent decimal number,

(356.25)₈ = 192 + 40 + 6 + 0.25 + 0.078 = (238.328)₁₀

example 2

convert (527.322)₈ to its decimal equivalent.

solution

we can convert the given octal number to its equivalent decimal number as follows −

octal digits	positional weights	multiply	product
5	(8)²	5 × (8)²	320
2	(8)¹	2 × (8)¹	16
7	(8)⁰	7 × (8)⁰	7
.	.	.	.
3	(8)^-1	3 × (8)^-1	0.375
2	(8)^-2	2 × (8)^-2	0.0313
2	(8)^-3	2 × (8)^-3	0.004

add all the product terms to obtain the result,

(527.322)₈ = 320 + 16 + 7 + 0.375 + 0.0313 + 0.004 = (343.4103)₁₀

decimal to octal conversion

we can convert a mixed decimal number (having integer and fractional parts) to its equivalent octal number. for this, we convert the integer and fractional parts separately.

to convert the integer part of the given decimal number to octal, we divide the given decimal number successively by 8 till the quotient is 0. the octal equivalent is obtained by reading the remainders from bottom to top, where the last remainder will be the most significant digit.

to convert the fractional part of the given decimal number to octal, we multiply the given decimal fraction successively by 8 till the product is 0 or the desired accuracy is obtained. the fractional part of the equivalent octal number is obtained by reading the carries from top to bottom.

lets understand the decimal to octal conversion with the help of examples.

example

convert (589.278)₁₀ to octal.

solution

the given decimal number is a mixed number with 589 as integer part and 0.278 as fractional part. thus, we first convert the integer part to octal and then we convert the fractional part to octal.

converting integer part (589)₁₀ to octal −

	decimal	remainders
8	589
8	73	5
8	9	1
8	1	1
	0	1

reading the remainders from bottom to top, the equivalent octal of (589)₁₀ is (1115)₈.

converting the fractional part (0.278)₁₀ to octal −

decimal	product	carry
0.278 × 8	2.224	2
0.224 × 8	1.792	1
0.792 × 8	6.336	6
0.336 × 8	2.688	2

reading the carries from top to bottom to obtain the fractional part of the equivalent octal number, the result is (0.2162)₈.

thus, the equivalent octal number of (589.278)₁₀ is (1115.2162)₈.

hexadecimal to binary conversion

we can convert a hexadecimal number into its equivalent binary by using the mapping method. in this method, we replace each digit of the given hexadecimal number by its equivalent 4-bit binary group.

the following table shows the equivalent 4-bit binary group of each hexadecimal digit −

hexadecimal	binary
	(2)³ = 8	(2)² = 4	(2)¹ = 2	(2)⁰ = 1
0	0	0	0	0
1	0	0	0	1
2	0	0	1	0
3	0	0	1	1
4	0	1	0	0
5	0	1	0	1
6	0	1	1	0
7	0	1	1	1
8	1	0	0	0
9	1	0	0	1
a (10)	1	0	1	0
b (11)	1	0	1	1
c (12)	1	1	0	0
d (13)	1	1	0	1
e (14)	1	1	1	0
f (15)	1	1	1	1

let us understand the conversion of a hexadecimal number to binary number with the help of examples.

example 1

convert (3a94.c5d)₁₆ to binary equivalent.

solution

the given hexadecimal number can be converted into equivalent binary number as follows −

hexadecimal number	3	a	9	4	.	c	5	d
	3	10	9	4	.	12	5	13
4-bit binary equivalent	0011	1010	1001	0100	.	1100	0101	1101

thus, the binary equivalent of the given hexadecimal number is (0011101010010100.110001011101)₂.

example 2

convert (abd.2e)₁₆ to binary equivalent.

solution

the conversion of given hexadecimal number to its binary is done as follows −

hexadecimal number	a	b	d	.	2	e
	10	11	13	.	2	14
4-bit binary equivalent	1010	1011	1101	.	0010	1110

hence, the equivalent binary of (abd.2e)₁₆ is (101010111101.00101110)₂.

binary to hexadecimal conversion

to convert a given binary number to its equivalent hexadecimal number, we create groups of 4 bits each on both sides of the binary point. then, we replace each group of 4-bit binary by the equivalent hexadecimal digit.

let us understand the conversion of a binary number to its equivalent hexadecimal with the help of examples.

example 1

convert (1110111001101.111011)₂ to hexadecimal.

solution

the conversion of the given binary number to hexadecimal equivalent is done as follows −

4-bit group	1	1101	1100	1101	.	1110	11
	0001	1101	1100	1101	.	1110	1100
hexadecimal equivalent	1	d	c	d	.	e	c

thus, the hexadecimal equivalent of the given binary number is (1dcd.ec)₁₆.

example 2

convert (110111110111.1100)₂ to hexadecimal.

solution

we can convert the given binary number into hexadecimal equivalent as follows −

4-bit group	1101	1111	0111	.	1100
hexadecimal equivalent	d	f	7	.	c

thus, the hexadecimal equivalent of (110111110111.1100)₂ is (df7.c)₁₆.

hexadecimal to decimal conversion

to convert a hexadecimal number to its equivalent decimal number, we multiply each digit in the hexadecimal number by its positional weight and then add all the product terms to obtain the final result.

the step-by-step procedure to convert a hexadecimal number to its equivalent decimal number is explained below −

step 1 − write the positional weights for each hexadecimal digit.

step 2 − multiply each hexadecimal digit with its positional weight.

step 3 − add the product terms to obtain the equivalent decimal number.

let us see some examples to understand the conversion of hexadecimal to decimal number.

example 1

convert (5ab2.8c)₁₆ to decimal equivalent.

solution

the conversion of the given hexadecimal number to its decimal equivalent is given below −

hex digits	decimal equiv.	positional weights	multiply	product
5	5	(16)³	5 × (16)³	20480
a	10	(16)²	10 × (16)²	2560
b	11	(16)¹	11 × (16)¹	176
2	2	(16)⁰	2 × (16)⁰	2
.	.	.	.	.
8	8	(16)^-1	8 × (16)^-1	0.5
c	12	(16)^-2	12 × (16)^-2	0.0468

add all the product terms to obtain the equivalent decimal,

(5ab2.8c)₁₆ = 20480 + 2560 + 176 + 2 + 0.5 + 0.0468 = (23218.5468)₁₀

example 2

convert (1af.2)₁₆ to decimal.

solution

the decimal equivalent of the given hexadecimal number can be obtained as follows −

hex digits	decimal equiv.	positional weights	multiply	product
1	1	(16)²	1 × (16)²	256
a	10	(16)¹	10 × (16)¹	160
f	15	(16)⁰	15 × (16)⁰	15
.	.	.	.	.
2	2	(16)^-1	2 × (16)^-1	0.125

adding the product terms to obtain the equivalent decimal number,

(1af.2)₁₆ = 256 + 160 + 15 + 0.125 = (431.125)₁₀

decimal to hexadecimal conversion

if a mixed decimal number is given that has integer and fraction parts. then, to convert the given decimal number to its equivalent hexadecimal, we convert integer and fraction parts separately.

to convert the integer part, we successively divide the decimal integer by 16 till the quotient is 0. the integer part of the equivalent hexadecimal is obtained by reading the remainders from bottom to top.

to convert the fractional part, we multiply the decimal fractional number by 16 till the product is 0 or till the desired accuracy is obtained. the fractional part of the equivalent hexadecimal is obtained by reading the carries from top to bottom.

let us see some examples to understand the decimal to hexadecimal conversion.

example

convert (524.26)₁₀ to hexadecimal.

solution

the given decimal number is a mixed number. hence, we have to convert its integer and fractional parts separately.

converting integer part (524)₁₀ to hexadecimal −

	decimal	remainders
16	524
16	32	12 (c)
16	2	0
	0	2

reading the remainder from bottom to top to obtained the hexadecimal equivalent, the result is (20c)₁₆.

converting fractional part (0.26)₁₀ to hexadecimal −

decimal	product	carry
0.26 × 16	4.16	4
0.16 × 16	2.56	2
0.56 × 16	8.96	8
0.96 × 16	15.36	15 (f)

reading the carries from top to bottom to obtain the equivalent hexadecimal number, the result is (0.428f)₁₆.

thus, the hexadecimal equivalent of the decimal number (524.26)₁₀ is (20c.428f)₁₆.

octal to hexadecimal conversion

the conversion of octal to hexadecimal is very simple. we first convert the given octal number to binary and then the binary number to the hexadecimal.

the step-by-step process to convert a given octal number to its equivalent hexadecimal is given below −

step 1 − convert each digit of the given octal number to its equivalent binary of 3-bits.

step 2 − make groups of 4 bits each of the obtained binary number.

step 3 − convert each 4-bit binary group to its equivalent hexadecimal.

let us see some examples to understand the conversion of octal to hexadecimal.

example 1

convert (742.35)₈ to hexadecimal.

solution

the conversion of given octal number to hexadecimal is explained below −

octal digits	3-bit binary	4-bit binary	hex digits
7	111	0001	1
4	100	1110	e
2	010	0010	2
.	.	.	.
3	011	0111	7
5	101	0100	4

thus, the hexadecimal equivalent of the given octal number is (1e2.74)₁₆.

example 2

convert (1523.742)₈ to hexadecimal.

solution

the following table demonstrates the conversion of given octal number to hexadecimal −

octal digits	3-bit binary	4-bit binary	hex digits
1	001	0000	0
5	101	0011	3
2	010	0101	5
3	011	0011	3
.	.	.	.
7	111	1111	f
4	100	0001	1
2	010	0000	0

hence, the hexadecimal equivalent of the given octal number is (353.f1)₁₆.

hexadecimal to octal conversion

the hexadecimal to octal conversion can be perform in the same way as the octal to hexadecimal as explained above. to convert a given hexadecimal number to octal number, we first convert the given hexadecimal number to binary and then the binary number to the octal.

the step-by-step procedure to convert a hexadecimal number to its equivalent octal number is explained below −

step 1 − convert each hexadecimal digit to its equivalent 4-bit binary.

step 2 − make groups of 3-bits each of the obtained binary number.

step 3 − convert each 3-bit binary group to its equivalent octal number.

the following examples demonstrate the method of converting a given hexadecimal number to its equivalent octal number.

example 1

convert (b3a9.5f)₁₆ to octal.

solution

the conversion of the given hexadecimal number to its equivalent octal number is explained below −

hex digits			b	3	a	9	.	5	f
4-bit binary			1011	0011	1010	1001	.	0101	1111
3-bit binary	001	011	001	110	101	001	.	010	111	110
octal digits	1	3	1	6	5	1	.	2	7	6

thus, the octal equivalent of the given hexadecimal number is (131651.276)₈.

example 2

convert (ac.f)₁₆ to octal.

solution

the conversion of given hexadecimal number to its equivalent octal number is demonstrated below −

hex digits		a	c	.	f
		10	12	.	15
4-bit binary		1010	1100	.	1111
3-bit binary	010	101	100	.	111	100
octal digits	2	5	4	.	7	4

hence, the octal equivalent of the given hexadecimal number is (254.74)₈.

conclusion

we can convert a given number from one base to another. number system conversion is one the important operations in the field of digital electronics, as it allows to represent the same information in different formats. in this chapter, we explained all the possible number system conversions with the help of examples.

we can categorize binary numbers into two groups unsigned numbers and signed numbers. read this chapter to learn how signed and unsigned binary numbers are represented. we will also explain how you can find out the 1's and 2's complement form of signed binary numbers.

unsigned numbers

unsigned numbers contain only magnitude of the number. they dont have any sign. that means all unsigned binary numbers are positive. as in decimal number system, the placing of positive sign in front of the number is optional for representing positive numbers. therefore, all positive numbers including zero can be treated as unsigned numbers if positive sign is not assigned in front of the number.

signed numbers

signed numbers contain both sign and magnitude of the number. generally, the sign is placed in front of number. so, we have to consider the positive sign for positive numbers and negative sign for negative numbers. therefore, all numbers can be treated as signed numbers if the corresponding sign is assigned in front of the number.

if sign bit is zero, which indicates the binary number is positive. similarly, if sign bit is one, which indicates the binary number is negative.

representation of un-signed binary numbers

the bits present in the un-signed binary number holds the magnitude of a number. that means, if the un-signed binary number contains n bits, then all n bits represent the magnitude of the number, since it doesnt have any sign bit.

example

consider the decimal number 108. the binary equivalent of this number is 1101100. this is the representation of unsigned binary number.

(108)₁₀ = (1101100)₂

it is having 7 bits. these 7 bits represent the magnitude of the number 108.

representation of signed binary numbers

the most significant bit (msb) of signed binary numbers is used to indicate the sign of the numbers. hence, it is also called as sign bit. the positive sign is represented by placing 0 in the sign bit. similarly, the negative sign is represented by placing 1 in the sign bit.

if the signed binary number contains n bits, then (n-1) bits only represent the magnitude of the number since one bit (msb) is reserved for representing sign of the number.

there are three types of representations for signed binary numbers

sign-magnitude form
1s complement form
2s complement form

representation of a positive number in all these 3 forms is same. but, only the representation of negative number will differ in each form.

consider the positive decimal number +108. the binary equivalent of magnitude of this number is 1101100. these 7 bits represent the magnitude of the number 108. since it is positive number, consider the sign bit as zero, which is placed on left most side of magnitude.

(+108)₁₀ = (01101100)₂

therefore, the signed binary representation of positive decimal number +108 is . so, the same representation is valid in sign-magnitude form, 1s complement form and 2s complement form for positive decimal number +108.

sign-magnitude form

in sign-magnitude form, the msb is used for representing sign of the number and the remaining bits represent the magnitude of the number. so, just include sign bit at the left most side of unsigned binary number. this representation is similar to the signed decimal numbers representation.

example

consider the negative decimal number -108. the magnitude of this number is 108. we know the unsigned binary representation of 108 is 1101100. it is having 7 bits. all these bits represent the magnitude.

since the given number is negative, consider the sign bit as one, which is placed on left most side of magnitude.

(108)₁₀ = (11101100)₂

therefore, the sign-magnitude representation of -108 is 11101100.

1s complement form

the 1s complement of a number is obtained by complementing all the bits of signed binary number. so, 1s complement of positive number gives a negative number. similarly, 1s complement of negative number gives a positive number.

that means, if you perform two times 1s complement of a binary number including sign bit, then you will get the original signed binary number.

example

consider the negative decimal number -108. the magnitude of this number is 108. we know the signed binary representation of 108 is 01101100.

it is having 8 bits. the msb of this number is zero, which indicates positive number. complement of zero is one and vice-versa. so, replace zeros by ones and ones by zeros in order to get the negative number.

(108)₁₀ = (10010011)₂

therefore, the 1s complement of (108)₁₀ is (10010011)₂.

2s complement form

the 2s complement of a binary number is obtained by adding one to the 1s complement of signed binary number. so, 2s complement of positive number gives a negative number. similarly, 2s complement of negative number gives a positive number.

that means, if you perform two times 2s complement of a binary number including sign bit, then you will get the original signed binary number.

example

consider the negative decimal number -108.

we know the 1s complement of (108)₁₀ is (10010011)₂

2s compliment of (108)₁₀ = 1s compliment of (108)₁₀ + 1.

= 10010011 + 1

= 10010100

therefore, the 2s complement of (108)₁₀ is (10010100)₂.

binary arithmetic is one of the fundamental concepts in the field of digital electronics and computer engineering. it is basically the mathematics of binary numbers allow to perform various arithmetic operations on binary numbers. we know that the binary number system has two digits, i.e., 0 and 1 which are used to represent the on or off states of the digital systems. hence, binary arithmetic forms the foundation of the digital computing.

in this chapter, we will discuss the following four main binary arithmetic operations −

binary addition
binary subtraction
binary multiplication
binary division

lets discuss each of these binary arithmetic operations in detail along with solved examples.

binary addition

in binary arithmetic, the process of adding two binary numbers is called binary addition. where, the binary numbers consist of only 0 and 1. in the binary addition, a carry is generated when the sum is greater than 1.

rules of binary addition

the addition of two binary numbers is performed according to these rules of binary arithmetic −

$$\mathrm{0 \: + \: 0 \: = \: 0}$$

$$\mathrm{0 \: + \: 1 \: = \: 1}$$

$$\mathrm{1 \: + \: 0 \: = \: 1}$$

$$\mathrm{1 \: + \: 1 \: = \: 10 \: (sum \: = \: 0 \: & \: carry \: = \: 1}$$)

let us consider some examples to understand the binary addition.

example 1

add two binary numbers, 1101 and 1110.

solution

the binary addition of the given binary numbers is described below −

explanation

add 1 (rightmost bit of first number) and 0 (rightmost bit of the second number). it gives 1 + 0 = 1 (thus, write down 1 as sum bit).

add 0 (second rightmost bit of first number) and 1 (second rightmost bit of the second number). it gives 0 + 1 = 1 (write down 1 as sum bit).

add 1 (third rightmost bit of first number) and 1 (third rightmost bit of second number). it gives 1 + 1 = 10 (write down 0 as sum and 1 as carry).

add 1 (leftmost bit of the first number), 1 (leftmost bit of second number) and 1 (carry). it gives 1 + 1 + 1 = 11 (write down 1 as sum and 1 as carry).

write the end around carry 1 in the sum.

thus, the result is 11011.

example 2

add 1010 and 11011.

solution

the binary addition of given numbers is explained below −

explanation

add 0 (rightmost bit of first number) and 1 (rightmost bit of second number). it gives 0 + 1 = 1 (write down 1 as sum).

add 1 (second rightmost bit of first number) and 1 (second rightmost bit of second number). it gives 1 + 1 = 10 (write down 0 as sum and 1 as carry).

add 0 (third rightmost bit of first number), 0 (third rightmost bit of second number), and 1 (carry). it gives 0 + 0 + 1 = 1 (write down 1 as sum).

add 1 (leftmost bit of first number) and 1 (second leftmost bit of second number). it gives 1 + 1 = 10 (write down 0 as sum and 1 as carry).

add 1 (leftmost bit of second number) and 1 carry. it gives 1 + 1 = 10 (write down 0 as sum and 1 as the end around carry).

hence, the sum of 1010 and 11011 is 100101.

binary subtraction

in binary arithmetic, binary subtraction is a mathematical operation used to find the difference between two binary numbers.

in binary subtraction, each bit of the binary numbers is subtracted, starting from the rightmost bit.

also, a borrow bit can be taken from higher bits if require.

rules of binary subtraction

the binary subtraction is performed as per the following rules of binary arithmetic −

$$\mathrm{0 \: \: 0 \: = \: 0}$$

$$\mathrm{1 \: \: 0 \: = \: 1}$$

$$\mathrm{0 \: \: 1 \: = \: 1 \: (borrow \: 1 \: from \: the \: next \: higher \: bit)}$$

$$\mathrm{1 \: \: 1 \: = \: 0}$$

let us see some examples to understand the binary subtraction.

example 1

subtract 1100 from 1101.

solution

the subtraction of given binary numbers is given below −

1101 1100 = 0001

explanation

subtract 0 (rightmost bit of second number) from 1 (rightmost bit of first number). it gives 1 0 = 1 (write down 1 as difference).

subtract 0 (second rightmost bit of second number) from 0 (second rightmost bit of first number). it gives 0 0 = 0 as result.

subtract 1 (third rightmost bit of second number) from 1 (third rightmost bit of first number). it gives 1 1 = 0 as result.

subtract 1 (leftmost bit of second number) from 1 (leftmost bit of first number). it gives 1 1 = 0 as result.

thus, the difference of 1101 and 1100 is 0001.

example 2

subtract 101 from 1111.

solution

the subtraction of given binary numbers is explained below −

explanation

subtract rightmost bits: 1 1 = 0

subtract second rightmost bits: 1 1 = 1

subtract third rightmost bits: 1 1 = 0

subtract leftmost bits: 1 0 = 1

thus, the result is 1010.

example 3

subtract 1011 from 1101.

solution

the binary subtraction of 1101 and 1011 is given below −

explanation

subtract rightmost bits: 1 1 = 0.

subtract second rightmost bits: 0 1 = 1. a borrow 1 is taken from the next higher bit.

subtract third rightmost bits: 0 0 = 0. the 1 borrow is given to previous bit.

subtract leftmost bits: 1 1 = 0.

thus, the difference of 1101 and 1011 is 0010.

binary multiplication

in binary arithmetic, binary multiplication is the process of multiplying two binary numbers and obtain their product.

in binary multiplication, we multiply each bit of one binary number by each bit of another binary number and then add the partial products to obtain the final product.

rules of binary multiplication

the multiplication of two binary numbers is performed as per the following rules of binary arithmetic −

$$\mathrm{0 \: \times \: 0 \: = \: 0}$$

$$\mathrm{0 \: \times \: 1 \: = \: 0}$$

$$\mathrm{1 \: \times \: 0 \: = \: 0}$$

$$\mathrm{1 \: \times \: 1 \: = \: 1}$$

it is clear that the binary multiplication is similar to the decimal multiplication. let us understand the binary multiplication with the help of solved examples.

example 1

multiply 1101 and 11.

solution

the binary multiplication of given numbers is described below −

explanation

multiply the rightmost bit of the second number, 1 by each bit of the first number (1101).

now, shift the partial product one position to the left to perform the next multiplication.

multiply the leftmost bit of the second number, 1 by each bit of the first number (1101).

finally, sum up all the partial products to obtain the final product.

hence, the product of 1101 and 11 is 100111.

example 2

multiply 11011 and 110.

solution

the multiplication of given binary numbers is demonstrated below −

explanation

multiply rightmost bit of the second number (0) by each bit of the first binary number (11011).

shift the partial product one position to the left.

multiply the second rightmost bit of the second number (1) by each bit of the first binary number (11011).

again, shift the partial product one position to the left.

multiply the leftmost bit of the second number (1) by each bit of the first number.

then, sum up all the partial products to obtain the final product.

hence, the product of 11011 and 110 is 10100010.

binary division

binary division is one of the basic arithmetic operations used to find the quotient and remainder when dividing one binary number by another.

rules of binary division

the following rules of binary arithmetic are utilized while diving one binary number by another −

$$\mathrm{0 \: \div \: 0 \: = \: undefined}$$

$$\mathrm{0 \: \div \: 1 \: = \: 0 \: with \: remainder \: = \: 0}$$

$$\mathrm{1 \: \div \: 0 \: = \: undefined}$$

$$\mathrm{1 \: \div \: 1 \: = \: 1 \: with \: remainder \: = \: 0}$$

binary division procedure

start dividing from the leftmost bits of the dividend by the divisor.
multiply the quotient obtained by the divisor and subtract from the dividend.
bring down the next bits of the dividend and repeat the division process until all the bits of given divided are used.

let us consider some solved examples to understand the binary division.

example 1

divide 110011 by 11.

solution

the division of the given binary numbers is explained below −

110011 11 = 10001

in this example of binary division, the quotient obtained is 10001 and the remainder is 0.

example 2

divide 11011 by 10.

solution

the binary division of 11011 by 10 is explained below −

11011 10 = 1101

in this example, the quotient is 1101 and the remainder is 1.

conclusion

binary arithmetic involves arithmetic operations performed on binary numbers. in general, the four basic arithmetic operations namely addition, subtraction, multiplication, and division are performed on binary numbers.

in this chapter, we explained the rules and procedure to perform all the four basic binary arithmetic operations along with solved examples.

in this chapter, let us discuss about the basic arithmetic operations, which can be performed on any two signed binary numbers using 2s complement method. the basic arithmetic operations are addition and subtraction.

addition of two signed binary numbers

consider the two signed binary numbers a & b, which are represented in 2s complement form. we can perform the addition of these two numbers, which is similar to the addition of two unsigned binary numbers. but, if the resultant sum contains carry out from sign bit, then discard (ignore) it in order to get the correct value.

if resultant sum is positive, you can find the magnitude of it directly. but, if the resultant sum is negative, then take 2s complement of it in order to get the magnitude.

example 1

let us perform the addition of two decimal numbers +7 and +4 using 2s complement method.

the 2s complement representations of +7 and +4 with 5 bits each are shown below.

$$\mathrm{(+7)_{10} \: = \: (00111)_{2}}$$

$$\mathrm{(+4)_{10} \: = \: (00100)_{2}}$$

the addition of these two numbers is

$$\mathrm{(+7)_{10} \: + \: (+4)_{10} \: = \: (00111)_{2} \: + \: (00100)_{2}}$$

$$\mathrm{\rightarrow \: (+7)_{10} \: + \: (+4)_{10} \: = \: (01011)_{2}}$$

the resultant sum contains 5 bits. so, there is no carry out from sign bit. the sign bit 0 indicates that the resultant sum is positive. so, the magnitude of sum is 11 in decimal number system. therefore, addition of two positive numbers will give another positive number.

example 2

let us perform the addition of two decimal numbers -7 and -4 using 2s complement method.

the 2s complement representation of -7 and -4 with 5 bits each are shown below.

$$\mathrm{(7)_{10} \: = \: (11001)_{2}}$$

$$\mathrm{(4)_{10} \: = \: (11100)_{2}}$$

the addition of these two numbers is

$$\mathrm{(7)_{10} \: + \: (4)_{10} \: = \: (11001)_{2} \: + \: (11100)_{2}}$$

$$\mathrm{\rightarrow \: (7)_{10} \: + \: (4)_{10} \: = \: (110101)_{2}}$$

the resultant sum contains 6 bits. in this case, carry is obtained from sign bit. so, we can remove it

resultant sum after removing carry is (7)₁₀ + (4)₁₀ = (10101)₂.

the sign bit 1 indicates that the resultant sum is negative. so, by taking 2s complement of it we will get the magnitude of resultant sum as 11 in decimal number system. therefore, addition of two negative numbers will give another negative number.

subtraction of two signed binary numbers

consider the two signed binary numbers a & b, which are represented in 2s complement form. we know that 2s complement of positive number gives a negative number. so, whenever we have to subtract a number b from number a, then take 2s complement of b and add it to a. so, mathematically we can write it as

a - b = a + (2's complement of b)

similarly, if we have to subtract the number a from number b, then take 2s complement of a and add it to b. so, mathematically we can write it as

b - a = b + (2's complement of a)

so, the subtraction of two signed binary numbers is similar to the addition of two signed binary numbers. but, we have to take 2s complement of the number, which is supposed to be subtracted. this is the advantage of 2s complement technique. follow, the same rules of addition of two signed binary numbers.

example 1

let us perform the subtraction of two decimal numbers +7 and +4 using 2s complement method.

the subtraction of these two numbers is

$$\mathrm{(+7)_{10} \: \: (+4){10} \: = \: (+7)_{10} \: + \: (4)_{10}}$$

the 2s complement representation of +7 and -4 with 5 bits each are shown below.

$$\mathrm{(+7)_{10} \: = \: (00111)_{2}}$$

$$\mathrm{(+4)_{10} \: = \: (11100)_{2}}$$

$$\mathrm{\rightarrow \: (+7)_{10} \: + \: (+4)_{10} \: = \: (00111)_{2} \: + \: (11100)_{2} \: = \: (00011)_{2}}$$

here, the carry obtained from sign bit. so, we can remove it. the resultant sum after removing carry is

$$\mathrm{(+7)_{10} \: + \: (+4)_{10} \: = \: (00011)_{2}}$$

the sign bit 0 indicates that the resultant sum is positive. so, the magnitude of it is 3 in decimal number system. therefore, subtraction of two decimal numbers +7 and +4 is +3.

example 2

let us perform the subtraction of two decimal numbers +4 and +7 using 2s complement method.

the subtraction of these two numbers is

$$\mathrm{(+4)_{10} \: \: (+7)_{10} \: = \: (+4)_{10} \: + \: (7)_{10}}$$

the 2s complement representation of +4 and -7 with 5 bits each are shown below.

$$\mathrm{(+4)_{10} \: = \: (00100)_{2}}$$

$$\mathrm{(-7)_{10} \: = \: (11001)_{2}}$$

$$\mathrm{\rightarrow \: (+4)_{10} \: + \: (-7)_{10} \: = \: (00100)_{2} \: + \: (11001)_{2} \: = \: (11101)_{2}}$$

here, carry is not obtained from sign bit. the sign bit 1 indicates that the resultant sum is negative. so, by taking 2s complement of it we will get the magnitude of resultant sum as 3 in decimal number system. therefore, subtraction of two decimal numbers +4 and +7 is -3.

what is octal arithmetic?

in digital electronics, octal numbers are widely used in system designing, encoding, decoding, etc. octal arithmetic can be defined as the mathematics that provides a set of rules and operators to manipulate octal numbers. in other words, a mathematical system of numerical calculations that utilizes octal numbers is referred to as octal arithmetic.

in octal arithmetic, we can perform the following four basic arithmetic operations −

octal addition
octal subtraction
octal multiplication
octal division

in digital electronic systems, octal numbers are used to represent binary information and data in a more compact form, as an octal digit can represent a group three binary digits or bits. therefore, the understanding of octal arithmetic is important in the study of digital electronics.

let us discuss each of the four octal arithmetic operations one-by-one in detail with the help of examples.

octal addition

in octal arithmetic, octal addition is one of the basic arithmetic operations used to add two or more octal numbers to produce their sum. octal addition is similar to decimal addition. but, in the case of octal addition, a carry is generated to pass over to the next column when the sum is equal to or greater than 8.

let us see some solved examples to understand the process of octal addition.

example 1

add (315)₈ and (222)₈.

solution

the addition of octal numbers 315 and 222 is given below −

explanation

add the octal digits in the rightmost column: 5 + 2 = 7. write down the digit 7 as result.

move to the second column and add the octal digits 1 and 2: 1 + 2 = 3. write down the digit 3 as result.

move to the next column and add the octal digits in the third column: 3 + 2 = 5. write down the digit 5 as result.

hence, the final result of octal addition of 315 and 222 is 537.

example 2

perform the octal addition (372)₈ + (716)₈.

solution

the addition of given octal numbers is explained below −

explanation

add the octal digits in rightmost column: 2 + 6 = (10)₈. thus, write down the last digit (0) as the result and carry over the 1 to the next column.

move to the second column and add the octal digits including the carry-over from the previous step: 7 + 1 + 1 = (11)₈. write the last digit (1) as the result and carry over left 1 to the next column.

move to the third column and add the octal digits along with the carry from the previous step: 3 + 7 + 1 = 13. no digits left to add. thus, write down the result.

hence, the final result of the octal addition is 1310.

octal subtraction

octal subtraction is another basic arithmetic operation performed on octal numbers. it is used to find the difference between two octal numbers.

let an octal subtraction as (x)₈ - (y)₈, if the digit x is smaller than the digit y, a borrow 1 from the next higher order position is taken to perform the octal subtraction.

let us see some solved examples to understand the octal subtraction.

example 1

subtract (213)₈ from (325)₈.

solution

the given octal subtraction is performed below −

explanation

start subtracting from the digits in the rightmost column: 5 3 = 2. write down the digit 2 as result.

move to the next column and subtract the digits: 2 1 = 1. write down the digit as result.

move to the next column and subtract the octal digits: 3 2 = 1. write down the digit 1 as result.

thus, the final result of the given octal subtraction is (112)₈.

example 2

subtract (125)₈ from (317)₈.

solution

the octal subtraction of numbers 317₈ and 125₈ is explained below −

explanation

subtract rightmost digits: 7 5 = 2. write down the digit 2 as result.

move to the second column and subtract digits: 1 2. since 1 is less than 2, a borrow 1 from the next higher digit is taken that makes it 11. thus, the octal subtraction is 11 2 = 7. write down the octal digit 7 as result.

move to the leftmost column and subtract the digits: 2 1 = 1. write down the digit 1 as result.

thus, the final result of the subtraction is (172)₈.

octal multiplication

octal multiplication is the third basic arithmetic operation performed on octal numbers. it is used find the product of two octal numbers.

the octal multiplication is performed by multiplying each digit of one octal number by each digit of another octal number. the final result is obtained by summing up all the partial products of the multiplication.

the following numerical examples demonstrate the method of performing octal multiplication.

example 1

multiply (375)₈ by (5)₈.

solution

the multiplication of given octal numbers is explained below −

explanation

multiply the octal digit 5 by each digit of the octal number 375. write down the results of multiplication to get the final product that is (2361)₈.

example 2

perform the octal multiplication of (624)₈ and (25)₈.

solution

the multiplication of given octal numbers is explained below −

explanation

multiply the rightmost digit (5)₈ of the second octal number 25 by each digit of the first octal number 624 and write down the partial products.

move to the next digit (2)₈ of the octal number 25 and multiply it by each digit of the octal number 624. shift one position to the left and write down the partial product.

add all the partial products to obtain the final result, that is (20444)₈.

octal division

octal division is one of the basic arithmetic operations that can be performed on octal numbers to find their quotient and remainder.

the step-by-step procedure of octal division is described below −

step 1 − start by dividing the leftmost digits of the dividend by the divisor.

step 2 − multiply the quotient obtained by the divisor and subtract the product from the dividend.

step 3 − bring down the next octal digits of the dividend and repeat the above two steps until all the digits in the dividend are used.

let us understand the division of octal numbers through some solved examples.

example 1

divide (1275)₈ by (3)₈.

solution

the octal division of given numbers is shown below −

in this example, the division of octal number (1275)₈ by (3)₈ gives (351)₈ as quotient and (2)₈ as remainder.

let us take another example for a better understanding of octal division.

example 2

perform octal division of (1365)₈ by (5)₈.

solution

the octal division of given numbers is described below −

in this example of octal division, the quotient is (227)₈ and the remainder is (2)₈.

we can also perform octal arithmetic operations by converting them to binary form. as we know, an octal digit can be represented by a group of 3 binary digits or bits.

the binary representation of each octal digit is given in the following table −

octal digit	3-bit binary
0	000
1	001
2	010
3	011
4	100
5	101
6	110
7	111

let us see some examples to learn the octal arithmetic operations through binary conversion.

octal addition through binary conversion

the addition of two octal numbers through binary conversion can be performed as per the following steps −

step 1 − convert the given octal number to their binary equivalent.

step 2 − add the obtained binary numbers.

step 3 − convert final result back to the octal format.

example

add (75)₈ and (14)₈ through binary conversion.

solution

converting the given octal numbers to their binary equivalents.

(75)₈ = (111 101)₂

(14)₈ = (001 100)₂

adding the octal numbers in their binary format,

converting the sum from binary to octal to obtain the final result,

(001 001 001)₂ = (111)₈

octal subtraction through binary conversion

to perform octal subtraction of two numbers through binary conversion, we first convert them to their binary equivalent, then perform subtraction according to the rules of binary subtraction, and finally convert the final result back to the octal number system.

here is an example that demonstrates how you can perform octal subtraction through binary conversion.

example

subtract (16))₈ from (47)₈ by converting in the binary equivalent.

solution

converting the given octal numbers to their equivalent binary,

(47)₈ = (100 111)₂

(16)₈ = (001 110)₂

subtracting the numbers using the rules of binary subtraction,

converting the result back to the octal number system,

(011 001)₂ = (31)₈

octal multiplication through binary conversion

just like addition and subtraction, we can also perform the multiplication of octal numbers by converting them into their equivalent binary. the following example demonstrates how you can perform octal multiplication through binary conversion.

example

multiply (417)₈ by (3)₈ in binary form.

solution

converting the given octal numbers to binary,

(417)₈ = (100 001 111)₂

(3)₈ = (011)₂

multiplying the obtained binary numbers,

octal multiplication through binary conversion

converting the result back to the octal format,

(1 100 101 101)₂ = (1455)₈

octal division through binary conversion

to perform octal division through binary conversion, we first convert the given octal number to their equivalent binary, then perform their division as per the rules of binary division, and finally convert the result back to the octal form.

the following example explains how you can perform octal division through binary conversion.

example

divide (547)₈ by (5)₈ using binary conversion method.

solution

converting the given octal numbers to their binary equivalents,

(547)₈ = (101 100 111)₂

(5)₈ = (101)₂

performing binary division as per the rules of binary division arithmetic,

converting the binary result back to the octal format,

quotient = (1 000 111)₂ = (107)₈

remainder = (100)₂ = (4)₈

conclusion

in this chapter, we explained various arithmetic operations such as addition, subtraction, multiplication and division of octal numbers.

we also covered the binary method of octal arithmetic operations in which we first convert the given octal numbers to their binary equivalent, and then perform the arithmetic operations, and finally convert the binary result back to the octal format.

what is hexadecimal arithmetic?

in digital electronics, hexadecimal numbers are used to represent binary information in more compact form, as one hexadecimal digit can represent a group of 4 binary digits. therefore, hexadecimal numbers and arithmetic operation on them play a vital role in the field of digital electronics.

hexadecimal arithmetic is a mathematical system that allows to perform arithmetic operations such as addition, subtraction, multiplication, and division of hexadecimal or base-16 numbers.

in this chapter, we will cover the following four basic hexadecimal arithmetic operations −

hexadecimal addition
hexadecimal subtraction
hexadecimal multiplication
hexadecimal division

lets understand each of the hexadecimal arithmetic operations in detail with the help of examples.

hexadecimal addition

hexadecimal addition is one of the basic arithmetic operations performed on hexadecimal numbers to determine their sum. basically, hexadecimal addition is similar to decimal addition. but in hexadecimal addition, a carry is generated to the next higher column if the sum is greater than or equal to 16.

let us see some solved examples to better understand the hexadecimal addition.

example 1

add (5a)₁₆ and (bf)₁₆.

solution

the addition of the given hexadecimal numbers is shown below −

(5a)₁₆ + (bf)₁₆ = (119)₁₆

explanation

start by adding the hexadecimal digits in the rightmost column: a + f = 10 + 15 = 25 = 16 + 9. here, 16 forms a carry to the next column. thus, the sum is 9 with a 1 as carry to the next column.

move to the next column and add the digits along with carry: 5 + b + 1 = 5 + 11 + 1 = 17 = 16 + 1. here, 16 forms a carry to the next column. thus, the sum is 1 with a carry 1. there are no digits left, hence carry will also be written as leftmost digit in the sum.

so, the hexadecimal sum of 5a and bf is 119.

example 2

add (abc)₁₆ and (2a9)₁₆.

solution

the hexadecimal sum of given numbers is shown below −

(abc)₁₆ + (2a9)₁₆ = (d65)₁₆

explanation

start by adding the digits in the rightmost column: c + 9 = 12 + 9 = 21 = 16 + 1. here, 16 forms a carry. thus, the sum is 1 with a carry 1.

move to the next column and add the digits along with the carry from the previous step: b + a + 1 = 11 + 10 + 1 = 22 = 16 + 6. thus, the sum is 6 with a carry 1 to the next column.

move to the leftmost column and add the digits along with the carry from the previous step: a + 2 + 1 = 10 + 2 + 1 = 13. since, the sum is 13 which is less than 16, hence no carry is generated. in hexadecimal number system, 13 is represented by the letter d.

hence, the hexadecimal sum of abc and 2a9 = d65.

this is all about hexadecimal addition that involves the addition of digits of the given hexadecimal numbers column by column. the most important point to keep in mind while performing hexadecimal addition is that a carry is generated to the next column when the sum in a particular column is greater than or equal to 16, i.e., base of the hexadecimal number system.

hexadecimal subtraction

hexadecimal subtraction is a basic arithmetic operation performed on hexadecimal numbers to determine the difference between them.

hexadecimal subtraction is similar to decimal subtraction. the only difference is that in hexadecimal subtraction, when the minuend digit is smaller than the subtrahend digit, a borrow 1, which is equivalent to 16, is taken from the higher column digit.

let us understand the hexadecimal subtraction with the help of solved examples.

example 1

subtract (125)₁₆ from (a57)₁₆.

solution

the subtraction of given hexadecimal numbers is given below −

(a57)₁₆ - (125)₁₆ = (932)₁₆

explanation

start subtracting the hexadecimal digits from rightmost column: 7 5 = 2. write down the result.

move to the next column and subtract the digits: 5 2 = 3. write down the digit 3 as difference.

move to the leftmost column and subtract the digits: a 1 = 10 1 = 9. write down the result as difference.

so, the hexadecimal difference of a57 and 125 is 932.

example 2

subtract (1da)₁₆ from (bc5)₁₆.

solution

the hexadecimal subtraction of bc5 and 1da is shown below −

(bc5)₁₆ - (1da)₁₆ = (9eb)₁₆

explanation

start by subtracting from the digits in rightmost column: 5 a. since 5 is less than a (10), so we have to borrow from the next higher-order digit. after borrowing from the next column (c), the digit 5 will become 5 + 16 (as 16 is equivalent to borrow 1) = 21. thus, 21 a = 11 (b). write down b as the difference.

move to the next column and subtract the digits: b d. again, b is smaller than d, so we take a borrow from the higher order digit b. after getting a borrow, b will become b + 16 = 27. thus, 27 d = 14 (e). write down the digit e as difference.

move to the leftmost column and subtract the digits: a 1 = 9. write down the result.

hence, the hexadecimal difference of bc5 and 1da is equal to 9eb.

these examples explain the process of subtracting two hexadecimal numbers. let us now discuss the third basic arithmetic operation on hexadecimal numbers i.e., hexadecimal multiplications.

hexadecimal multiplication

hexadecimal multiplication is an arithmetic operation used to determine the product of two hexadecimal numbers.

hexadecimal multiplication is similar to the decimal multiplication. but, in the case of hexadecimal multiplication, a carry is generated to the next column when the product is greater than or equal to 16.

the following examples demonstrate the process of multiplying two hexadecimal numbers.

example 1

multiply (a19)₁₆ by (b)₁₆.

solution

the multiplication of given hexadecimal numbers is shown below −

(a19)₁₆ times (b)₁₆ = (6f13)₁₆

explanation

multiply the digit (b)₁₆ with each digit of the number (a19)₁₆ and write down the result.

firstly, we multiply b by 9, it gives 99 = 96 + 3. hence, 3 is written as product and 96 as carry 6 (16 6 = 96) to the next column.

then, we multiply b by 1 and add the carry 6 to the product. it gives 17 = 16 + 1. here, the result is 1 and carry is 1.

finally, we multiply b by a and add the carry 1 overed from previous step to product. it gives 96 + 15 (f in hexadecimal). the result is f with a carry 6.

thus, the final hexadecimal product of a19 and b is 6f13.

example 2

multiply (abc)₁₆ by (29)₁₆.

solution

the multiplication of given hexadecimal numbers is shown below −

(abc)₁₆ times (29)₁₆ = (1b81c)₁₆

explanation

in this example, we first multiply the digit (9)₁₆ of the second number (29)₁₆ by each digit of the number (abc)₁₆. write down the partial product.

then, we multiply the digit (2)₁₆ of the number (29)₁₆ by each digit of the number (abc)₁₆. write down the partial product by shifting one position to the left.

finally, we sum up all the partial products to obtain the final result.

thus, the hexadecimal product of (abc)₁₆ and (29)₁₆ is (1b81c)₁₆.

hexadecimal division

hexadecimal division is the fourth basic arithmetic operation that we perform on base-16 numbers. in the hexadecimal division, we obtain two results namely, quotient and remainder.

the following steps are to be followed to perform the hexadecimal division −

step 1 − start diving from the leftmost digit of the dividend.
step 2 − multiply the obtained quotient by the divisor and subtract from the dividend.
step 3 − bring down the next significant digit or digits of the dividend.
step 4 − repeat the process explained in the above three steps until all the digits in the dividend are used.

the following examples demonstrate the process of performing hexadecimal division.

example 1

divide (a29)₁₆ by (5)₁₆.

solution

the hexadecimal division of a29 by 5 is given below −

in this hexadecimal division, we have obtained the quotient (208)₁₆ and remainder (1)₁₆.

example 2

divide (1ac)₁₆ by (a)₁₆.

solution

the hexadecimal division of given numbers is shown below −

in this example, we obtained the quotient (2a)₁₆ and the remainder (8)₁₆.

we explained the direct method of performing hexadecimal arithmetic operations. now let's see how we can perform all these four hexadecimal arithmetic operations through binary arithmetic.

as we know, each hexadecimal digit can be represented as group of four bits as shown in the following table.

hexadecimal	binary
0	0000
1	0001
2	0010
3	0011
4	0100
5	0101
6	0110
7	0111
8	1000
9	1001
a	1010
b	1011
c	1100
d	1101
e	1110
f	1111

let us now discuss hexadecimal arithmetic operations through binary conversion.

hexadecimal addition through binary conversion

in this method of adding two hexadecimal numbers, we first convert them to their equivalent binary format, then add the obtained binary numbers using rules of binary arithmetic, and finally convert the final result back to the hexadecimal format.

the following example demonstrates the process of hexadecimal addition through binary conversion.

example

add (a5c)₁₆ and (ccd)₁₆ through binary conversion.

solution

converting the given hexadecimal numbers to their binary equivalent,

(a5c)₁₆ = (1010 0101 1100)₂

(ccd)₁₆ = (1100 1100 1101)₂

adding the obtained binary numbers,

finally, converting the binary sum to its equivalent hexadecimal format to obtain the final result.

(0001 0111 0010 1001)₂ = (1729)₁₆

hence, the hexadecimal sum of (a5c)₁₆ and (ccd)₁₆ is (1729)₁₆.

hexadecimal subtraction through binary conversion

to subtract two hexadecimal numbers through binary conversion, we first convert the given hexadecimal numbers to their binary equivalent. then, subtract them as per the rules of binary arithmetic. finally, convert the final result back to the hexadecimal format.

here is an example demonstrating the process of hexadecimal subtraction through binary conversion.

example

subtract (ac2)₁₆ from (fea)₁₆ using binary arithmetic.

solution

converting the given hexadecimal numbers to their binary equivalent,

(fea)₁₆ = (1111 1110 1010)₂

(ac2)₁₆ = (1010 1100 0010)₂

subtracting the obtained binary numbers,

converting the difference back to the hexadecimal to obtain the final result,

(0101 0010 1000)₂ = (528)₁₆

hence, the hexadecimal difference of (fea)₁₆ and (ac2)₁₆ is (528)₁₆.

hexadecimal multiplication through binary conversion

we can also multiply two hexadecimal numbers by converting them into their binary equivalent. for this, we first convert the given hexadecimal numbers to their binary equivalent, then multiply the binary numbers as per the rules of binary arithmetic, and convert the result back to hexadecimal to obtain the final result.

the following example demonstrates the process of multiplying hexadecimal numbers through binary conversion.

example

multiply (a9c)₁₆ by (b)₁₆ through binary conversion.

solution

converting the given hexadecimal numbers to their equivalent binary,

(a9c)₁₆ = (1010 1001 1100)₂

(b)₁₆ = (1011)₂

multiplying the binary numbers,

hexadecimal multiplication binary conversion

converting the product back to the hexadecimal format,

(0111 0100 1011 0100)₂ = (74b4)₁₆

thus, the hexadecimal product of a9c and b is 74b4.

hexadecimal division through binary conversion

the hexadecimal division can also be performed using binary arithmetic. in this method, firstly, we convert the given hexadecimal numbers to their binary equivalent and then divide them as per the rules of binary division. at the end, we convert the result from binary format to hexadecimal to obtain the final result.

let us understand the hexadecimal division using binary arithmetic with the help of an example.

example

divide (ab8)₁₆ by (a)₁₆ using binary arithmetic.

solution

converting the given hexadecimal numbers to their binary equivalent,

(ab8)₁₆ = (1010 1011 1000)₂

(a)₁₆ = (1010)₂

dividing the obtained binary numbers,

converting the quotient and remainder to hexadecimal,

quotient = (0001 0001 0010)₂ = (112)₁₆

remainder = (0100)₂ = (4)₁₆

conclusion

in this chapter, we explained the four basic arithmetic operations (addition, subtraction, multiplication, and division) of hexadecimal numbers. we also discussed the binary method of hexadecimal arithmetic operations.

complement arithmetic is a system of mathematical techniques used in the field of digital electronics to perform various arithmetic operations mainly, subtraction.

here, we will cover the following most widely used types of complements in digital systems −

9's complement
10's complement
1's complement
2's complement
7's complement
8's complement
15's complement
16's complement

let us discuss each of these complements in detail along with their application in arithmetic operations.

what is 9's complement?

in digital electronics, the 9's complement is a type of complement used to perform subtraction of decimal numbers using a digital system. thus, 9's complement is related to the decimal number system.

9's complement is used to perform subtraction because it simplifies the subtraction operation.
the 9's complement of a given decimal number is found by subtracting each digit of the number from 9.

the following table shows the 9's complement of each decimal digit −

decimal digit	9's complement
0	9 0 = 9
1	9 1 = 8
2	9 2 = 7
3	9 3 = 6
4	9 4 = 5
5	9 5 = 4
6	9 6 = 3
7	9 7 = 2
8	9 8 = 1
9	9 9 = 0

let us understand it with the help of examples.

example 1

find the 9's complement of the decimal number 7824.450.

solution

here is the step-by-step process for finding 9's complement of the given decimal number −

the 9's complement of 7 = 9 7 = 2
the 9's complement of 8 = 9 8 = 1
the 9's complement of 2 = 9 2 = 7
the 9's complement of 4 = 9 4 = 5
the 9's complement of 4 = 9 4 = 5
the 9's complement of 5 = 9 5 = 4
the 9's complement of 0 = 9 0 = 9

thus, the 9's complement of the decimal number 7824.450 is 2175.549.

example 2

find the 9's complement of 45608.

solution

the 9's complement of the decimal number 45608 is given below −

the 9's complement of 4 = 9 4 = 5.
the 9's complement of 5 = 9 5 = 4.
the 9's complement of 6 = 9 6 = 3.
the 9's complement of 0 = 9 0 = 9.
the 9's complement of 8 = 9 8 = 1.

thus, the 9's complement of 45608 is 54391.

what is 10's complement?

in digital electronics, the 10's complement is another type of complement used to perform subtraction of decimal numbers. again, the purpose of the 10's complement is to simplify the decimal subtraction operation.

there are two methods for finding the 10's complement of a decimal number −

method i − to find the 10's complement of a given decimal number, firstly we find the 9's complement by subtracting each digit of the number from 9. then, we add 1 to the 9's complement to obtain the 10's complement, i.e.,

10s complement = 9s complement + 1

the 10's complement of each decimal digit using this method is given in the following table −

decimal digit	9's complement
0	9 0 = 9 + 1 = 10 = 0 (ignore the carry)
1	9 1 = 8 + 1 = 9
2	9 2 = 7 + 1 = 8
3	9 3 = 6 + 1 = 7
4	9 4 = 5 + 1 = 6
5	9 5 = 4 + 1 = 5
6	9 6 = 3 + 1 = 4
7	9 7 = 2 + 1 = 3
8	9 8 = 1 + 1 = 2
9	9 9 = 0 + 1 = 1

method ii − in this method, we can use the following formula to find the 10's complement of a given decimal number,

10s complement = 10ⁿ number

where, n is the number of digits in the decimal number.

let us understand the process of finding the 10's complement through examples.

example 1

find the 10's complement of the decimal number 4872.

solution

the 10's complement of 4872 can be determined as follows −

finding the 9's complement of 4872,

9999 4872 = 5127

adding 1 to the 9's complement to obtain the 10's complement,

5127 + 1 = 5128

so, the 10's complement of 4872 is 5128.

example 2

find the 10's complement of 2478.98.

solution

the 10's complement of 2478.98 can be found as given below −

finding the 9's complement of 2478.98,

9999.99 2478.98 = 7521.01

adding 1 to the 9's complement to obtain the 10's complement,

7521.01 + 1 = 7521.02

hence, the 10's complement of 7521.01 is 7521.02.

example 3

find the 10's complement of 58942.

solution

the 10's complement of 58942 is given below −

10's complement of 58942 = 10⁵ 58942

10's complement of 58942 = 100000 58942 = 41058

thus, the 10's complement of 58942 is 41058.

what is 1's complement?

in digital electronics, the 1's complement is a type of complement used to simplify the subtraction of binary numbers. also, the 1's complement is used to represent the negative of a given binary number.

we can find the 1's complement of a binary number by changing all the 0s to 1s and all the 1s to 0s in the number.

we can also find the 1's complement of a binary number by subtracting each bit of the number from 1.

however, there is a major issue associated with the 1's complement that is it has two representations for 0. where, 00000000 represents the positive zero and its 1's complement is 11111111 that represents 0, but it is called negative zero.

let us consider some examples to understand the process of finding the 1's complement of binary numbers.

example 1

find the 1's complement of 101101.

solution

the 1's complement of 101101 can be obtained as follows −

method i − by flipping each bit −

the 1's complement of 1 = 0
the 1's complement of 0 = 1
the 1's complement of 1 = 0
the 1's complement of 1 = 0
the 1's complement of 0 = 1
the 1's complement of 1 = 0

method ii − by subtract each bit from 1 −

111111 101101 = 010010

hence, the 1's complement of 101101 is 010010.

example 2

find the 1's complement of 101101101.

solution

the 1's complement of given binary number is,

1s complement = 111111111 101101101 = 010010010

so, the 1's complement of 101101101 is 010010010.

what is 2's complement?

in digital electronics, the 2's complement is a concept widely used to perform binary subtraction using a digital system.

here are the following three methods that can be used to determine the 2's complement of a given binary number −

method i − by finding the 1's complement and then adding 1 to the 1's complement, i.e.,

2s complement = 1s complement + 1

method ii − by subtracting the given binary number from 2ⁿ, i.e.,

2s complement = 2ⁿ number

where, "n" is the number of bits in the number.

method iii − starting from the least significant bit (lsb), copy down the bits up to and including the first 1 bit encountered and then complement the remaining bits.

let us understand the process of finding the 2's complement of binary numbers through examples.

example 1

find the 2's complement of 1100111.

solution

we can find the 2's complement of 1100111 as follows −

method i − using 1's complement −

1s complement of 1100111 = 0011000

adding 1 to 1's complement to obtain the 2's complement,

0011000 + 1 = 0011001

method ii − using 2's complement formula −

2's complement = 2⁷ 1100111 = 128 1100111

2's complement = 10000000 1100111 = 0011001

method iii − by copying down the bits starting from the lsb up to and including the first 1 bit −

example 2

find the 2's complement of 11001100.

solution

the 2's complement of 11001100 can be obtained as follows −

method i − using 1's complement −

1's complement of 11001100 = 00110011

2's complement = 1's complement + 1

2's complement = 00110011 + 1

therefore,

2s complement = 00110100

method ii − by subtracting the number from 2ⁿ −

2's complement = 2⁸ - 11001100

2's complement = 100000000 11001100 = 00110100

method iii − by copying down bits up to first 1 bit −

what is 7's complement?

in digital electronics, the 7's complement is a concept used to simplify the octal subtraction. the 7's complement of a given octal number can be obtained by subtracting each digit of the number from 7.

the 7's complement of each octal digit is given in the following table −

octal digit	7's complement
0	7 0 = 7
1	7 1 = 6
2	7 2 = 5
3	7 3 = 4
4	7 4 = 3
5	7 5 = 2
6	7 6 = 1
7	7 7 = 0

let us consider some examples to understand the process of finding 7's complement of an octal number.

example 1

find the 7's complement of the octal number 3152.

solution

the 7's complement of 3152 can be obtained as follows −

the 7's complement of 3 = 7 3 = 4.
the 7's complement of 1 = 7 1 = 6.
the 7's complement of 5 = 7 5 = 2.
the 7's complement of 2 = 7 2 = 5.

hence, the 7's complement of 3152 is 4625.

example 2

find the 7's complement of the octal number 427102.

solution

the 7's complement of the given number is determined as given below −

777777 427102 = 350675

thus, the 7's complement of 427102 is 350675.

what is 8's complement?

the 8's complement is another type of complement concept used to simplify the octal subtraction. actually, it is similar to that of 10's complement in the decimal number system.

we can find the 8's complement of a given octal number as follows −

find the 7's complement of the given octal number by subtracting each digit of the number from 7.
add 1 to the 7's complement.
result will be the 8's complement of the given octal number.

thus,

8s complement = 7s complement + 1

the following table shows the 8's complement of each octal digit −

octal digit	8's complement
0	7 0 = 7 + 1 = 10 = 0 (ignore the carry)
1	7 1 = 6 + 1 = 7
2	7 2 = 5 + 1 = 6
3	7 3 = 4 + 1 = 5
4	7 4 = 3 + 1 = 4
5	7 5 = 2 + 1 = 3
6	7 6 = 1 + 1 = 2
7	7 7 = 0 + 1 = 1

let us understand the process of finding the 8's complement with the help of examples.

example 1

find the 8's complement of 4257.

solution

the 8's complement of 4257 can be found as given below −

7's complement of 4257 = 7777 4257 = 3520

8's complement = 7's complement + 1

8's complement = 3520 + 1 = 3521

thus, the 8's complement of 4257 is 3521.

example 2

find the 8's complement of 77201.

solution

the 8's complement of given octal number can be determined as follows −

7's complement of 77201 = 77777 77201 = 00576

8's complement = 7's complement + 1

8's complement = 00576 + 1 = 00577

so, the 8's complement of 77201 is 00577.

what is 15's complement?

in hexadecimal number system, the 15's complement is a complement concept used to simplify the subtraction operation of hexadecimal numbers. the 15's complement is similar to the 9's complement in decimal number system.

to find the 15's complement of a given hexadecimal number, we subtract each digit of the number from 15 (f).

the 15's complement of each hexadecimal digit is given in the following table −

hexadecimal digit	15's complement
0	f 0 = f
1	f 1 = e
2	f 2 = d
3	f 3 = c
4	f 4 = b
5	f 5 = a
6	f 6 = 9
7	f 7 = 8
8	f 8 = 7
9	f 9 = 6
a	f a = 5
b	f b = 4
c	f c = 3
d	f d = 2
e	f e = 1
f	f f = 0

the following examples demonstrate the process of finding 15's complement of the hexadecimal numbers.

example 1

find the 15's complement of the hexadecimal number a259c.

solution

the 15's complement of a259c can be obtained as follows −

the 15's complement of a = f a = 5.
the 15's complement of 2 = f 2 = d.
the 15's complement of 5 = f 5 = a.
the 15's complement of 9 = f 9 = 6.
the 15's complement of c = f c = 3.

so, the 15's complement of a259c is 5da63.

example 2

find the 15's complement of 1bcfa.

solution

the 15's complement of the given hexadecimal number is,

fffff 1bcfa = e4305

so, the 15's complement of hexadecimal number 1bcfa is e4305.

what is 16's complement?

in hexadecimal arithmetic, we can also determine the 16's complement of a given hexadecimal number. the 16's complement is a concept used to simplify the subtraction operation of hexadecimal numbers.

we can determine the 16's complement of a given hexadecimal number as described below −

find the 15's complement of the given hexadecimal number.
add 1 to the 15's complement obtained. this gives the 16's complement of the hexadecimal number.

therefore,

16's complement = 15's complement + 1

the 16's complement of each hexadecimal digit is given in the following table −

hexadecimal digit	15's complement
0	f 0 = f + 1 = 10 = 0 (ignore the carry)
1	f 1 = e + 1 = f
2	f 2 = d + 1 = e
3	f 3 = c + 1 = d
4	f 4 = b + 1 = c
5	f 5 = a + 1 = b
6	f 6 = 9 + 1 = a
7	f 7 = 8 + 1 = 9
8	f 8 = 7 + 1 = 8
9	f 9 = 6 + 1 = 7
a	f a = 5 + 1 = 6
b	f b = 4 + 1 = 5
c	f c = 3 + 1 = 4
d	f d = 2 + 1 = 3
e	f e = 1 + 1 = 2
f	f f = 0 + 1 = 1

let us take some examples to understand the process of finding the 16's complement of hexadecimal numbers.

example 1

find the 16's complement of 1abdf7.

solution

the 16's complement of the given hexadecimal number can be determined as follows −

15's complement of 1abdf7 = ffffff 1abdf7 = e54208

16's complement = 15's complement + 1

16's complement = e54208 + 1 = e54209

thus, the 16's complement of 1abdf7 is e54209.

example 2

find the 16's complement of abc.

solution

the 16's complement of abc is,

15's complement of abc = fff abc = 543

16's complement = 15's complement + 1

16's complement = 543 + 1 = 544

thus, the 16's complement of abc is 544.

this is all about finding different types of complements used in digital electronics.

now, let us see their application in performing subtraction operations.

subtraction using 9's complement

the 9's complement can be used to perform subtraction of decimal numbers. in this method, the difference of two decimal numbers is obtained by adding the 9's complement of the subtrahend to the minuend.

let us understand the subtraction using 9's complement through an example.

example 1

subtract (517)₁₀ from (729)₁₀.

solution

in this example, we have,

minuend = 729

subtrahend = 517

finding the 9's complement of 517, we get

999 517 = 482

now, adding 729 and 482 to obtain the difference of 729 and 517, we get,

729 + 482 = 1211

there is an end around carry, indicating the result is positive and is obtained by adding the end around carry to the lsd of intermediate result to obtain the final result, i.e.,

211 + 1 = 212

so, the difference of 729 and 517 is 212.

example 2

subtract (203)₁₀ from (159)₁₀ using 9's complement method.

solution

in this example,

minuend = 159

subtrahend = 203

taking 9's complement of 203, we get,

999 203 = 796

adding 159 and 796, we get,

159 + 796 = 955

there is no end around carry. thus, the final result is negative and obtained by taking the 9's complement of 955, i.e.,

999 955 = 44

thus, the final result of subtraction 159 203 = 44.

subtraction using 10's complement

we can also perform decimal subtraction using 10's complement. the step-by-step procedure to perform decimal subtraction using 10's complement is given below −

step 1 − consider the decimal subtraction, x y. where, x is minuend and y is subtrahend.
step 2 − find 10's complement of y.
step 3 − add x and 10's complement of y.
step 4 − if there is an end-around carry, the result will be positive and final result is obtained by discarding the carry. if there is no end-around carry, it indicates that the result is negative and is obtained by taking 10's complement of the intermediate result and assign a negative sign before it.

let us understand the decimal subtraction using 10's complement with the help of examples.

example 1

subtract (599)₁₀ from (875)₁₀ using 10's complement arithmetic.

solution

in this example, we have,

minuend = 875

subtrahend = 599

finding 10's complement of 599, we get,

10s complement of 599 = 9s complement + 1

therefore,

10s complement of 599 = (999 599) + 1 = 401

adding 875 and 401, we get,

875 + 401 = 1276

there is an end-around carry, showing that the result is positive and is obtained by discarding the carry.

thus, the difference of 875 and 599 is 276.

example 2

subtract (307)₁₀ from (279)₁₀ using 10's complement arithmetic.

solution

we have,

minuend = 279

subtrahend = 307

taking 10's complement of 307, we get,

10s complement of 307 = (999 307) + 1 = 693

adding 279 and 693, we get,

279 + 693 = 972

there is no end-around carry, indicating that the result is negative. the final result is obtained by taking the 10's complement of 972 i.e.,

10's complement of 972 = (999 - 972) + 1 = 28

hence, the final result is 28.

subtraction using 1's complement

the 1's complement is used in binary subtraction operation.

the subtraction of two binary numbers, say x and y i.e., x y, can be performed using 1's complement as per the following steps −

step 1 − find the 1's complement of subtrahend (y).
step 2 − add x and 1's complement of y.
step 3 − if there is an end-around carry, it indicates the result is positive and final result is obtained by adding the end-around carry to the lsb of the intermediate result. if there is no end-around carry, the result is negative and obtained by taking 1's complement of the intermediate result and put a negative sign in front of it.

consider the following examples to understand the binary subtraction using 1's complement arithmetic.

example 1

subtract (111)₂ from (1011)₂ using 1's complement.

solution

in this example, we have,

minuend = 1011

subtrahend = 0111

finding 1's complement of subtrahend,

1s complement of 0111 = 1000

adding 1011 and 1000, we get,

1011 + 1000 = 1 0011

there is an end-around carry, indicating that the result is positive. the final result is obtained by adding this end-around carry to lsb of the intermediate result (0011) i.e.,

0011 + 1 = 0100

hence, the binary difference of 1011 and 111 is 100.

example 2

subtract (1100)₂ from (111)₂ using 1's complement arithmetic.

solution

we are given,

minuend = 0111

subtrahend = 1100

finding the 1's complement of the subtrahend,

1s complement of 1100 = 0011

adding 0111 and 0011, we get,

0111 + 0011 = 1010

there is no end-around carry, indicating that the result is negative and is obtained by taking 1's complement of 1010 i.e.,

1s complement of 1010 = 0101

hence, the binary difference of 111 and 1100 is -101.

subtraction using 2's complement

the 2's complement is also used to perform binary subtraction operation using digital systems. the step-by-step procedure to perform the subtraction of two binary numbers, say x and y, i.e., (x y) is given as follows −

step 1 − find the 2's complement of subtrahend (y).
step 2 − add x and 2's complement of y.
step 3 − if there is an end-around carry, it indicates the result is positive and the final result is obtained by ignoring the end-around carry. if there is no end-around carry, the result is negative and obtained by taking 2's complement of the intermediate result and put a negative sign in front of it.

let us see some examples to understand binary subtraction using 2's complement arithmetic.

example 1

subtract (101)₂ from (1100)₂ using 2's complement arithmetic.

solution

in this example, we are given,

minuend = 1100

subtrahend = 0101

taking 2's complement of the subtrahend, we get,

2's complement of 0101 = (1111 - 0101) + 1 = 1011

adding 1100 and 1011, we get,

1100 + 1011 = 1 0111

there is an end-around carry, indicating that the result is positive and the final result is obtained by ignoring this end around carry.

thus, the binary difference of 1100 and 101 is 111.

example 2

subtract (1010)₂ from (0110)₂ using 2's complement arithmetic.

solution

the given numbers are,

minuend = 0110

subtrahend = 1010

taking 2's complement of the subtrahend, we get,

2's complement of 1010 = (1111 - 1010) + 1 = 0110

adding minuend and 2's complement of subtrahend, we get,

0110 + 0110 = 1100

since, there is no end-around carry, indicating that the result is negative. the final result is obtained by taking 2's complement of intermediate result, i.e.,

2s complement of 1100 = (1111 - 1100) + 1 = 0100

thus, the binary difference of 0110 and 1010 is -100.

subtraction using 7's complement

the 7's complement arithmetic can be used to perform subtraction of octal numbers. here are the steps involved in performing octal subtraction using 7's complement.

let we want to subtract octal number y from x i.e., x y, then

step 1 − find the 7's complement of subtrahend (y).
step 2 − add x and 7's complement of y.
step 3 − if there is an end-around carry, it indicates the result is positive and the final result is obtained by adding the end-around carry to the intermediate result. if there is no end-around carry, the result is negative and is obtained by taking 7's complement of the intermediate result and put a negative sign in front of it.

let us understand octal subtraction using 7's complement arithmetic.

example 1

subtract (540)₈ from (721)₈ using 7's complement arithmetic.

solution

given numbers are,

minuend = 721

subtrahend = 540

taking 7's complement of the subtrahend,

7s complement of 540 = 777 540 = 237

adding 7's complement and minuend, we get,

721 + 237 = 1 160

there is an end-around carry, indicating that the result is positive and the final result is obtained by adding this end-around carry to the intermediate result, i.e.,

160 + 1 = 161

thus, the octal difference of 721 and 540 is 161.

example 2

subtract (310)₈ from (121)₈ using 7's complement method.

solution

in this example, the given numbers are,

minuend = 121

subtrahend = 310

taking 7's complement of the subtrahend, we get,

7s complement of 310 = 777 310 = 467

adding minuend and the 7's complement of the subtrahend, i.e.,

121 + 467 = 610

since, there is no end around carry, indicating the result is negative and is obtained by taking 7's complement of the intermediate result i.e.,

7s complement of 610 = 777 610 = 167

hence, the octal difference of 121 and 310 is -167.

subtraction using 8's complement

the 8's complement is another technique that used to perform octal subtraction. the step-by-step procedure to perform octal subtraction using 8's complement is explained below −

step 1 − if an octal subtraction is defined as x y. then, find the 8's complement of subtrahend (y).
step 2 − add x and 8's complement of y.
step 3 − if there is an end-around carry, it indicates the result is positive and the final result is obtained by ignoring the end-around carry. if there is no end-around carry, the result is negative and is obtained by taking the 8's complement of the intermediate result and put a negative sign in front of it.

let us understand the octal subtraction using 8's complement method through examples.

example 1

subtract (103)₈ from (712)₈ using 8's complement arithmetic.

solution

we are given,

minuend = 712

subtrahend = 103

finding the 8's complement of subtrahend, we get,

8s complement of 103 = (777 - 103) + 1 = 675

adding the minuend and 8's complement of subtrahend, we get,

712 + 675 = 1607

there is an end-around carry. the final result is obtained by ignoring the end-around carry.

thus, the octal difference of 712 and 103 is 607.

example 2

subtract (471)₈ from (206)₈ using the 8's complement method.

solution

in this example, we have,

minuend = 206

subtrahend = 471

finding the 8's complement of subtrahend,

8s complement of 471 = (777 - 471) + 1 = 307

adding the minuend and 8's complement of subtrahend, we get,

206 + 307 = 515

since, there is no end-around carry, hence the final result is negative and is obtained by taking the 8's complement of the intermediate result i.e.,

8's complement of 515 = (777 - 515) + 1 = 263

hence, the octal difference of 206 and 471 is -263.

subtraction using 15's complement

the 15's complement is used to perform subtraction of hexadecimal numbers. if we want to subtract a hexadecimal number y from x, then we follow the steps given below −

step 1 − find the 15's complement of subtrahend (y).
step 2 − add x and 15's complement of y.
step 3 − if there is an end-around carry, it shows the result is positive and the final result is obtained by adding the end-around carry to the intermediate result. if there is no end-around carry, the result is negative and is obtained by taking 15's complement of the intermediate result and put a negative sign in front of it.

the following examples demonstrate the process of performing hexadecimal subtraction using 15's complement arithmetic.

example 1

subtract (1920)₁₆ from (e57a)₁₆ using 15's complement arithmetic.

solution

the given numbers are,

minuend = e57a

subtrahend = 1920

finding 15's complement of the subtrahend,

15s complement of subtrahend = ffff 1920 = e6df

adding the minuend and 15's complement of subtrahend, we get,

e57a + e6df = 1 cc59

there is an end around carry showing that the result is positive and is obtained by adding the end-around carry to the intermediate result, i.e.,

cc59 + 1 = cc5a

hence, the hexadecimal difference of e57a and 1920 is cc5a.

example 2

subtract (dc25)₁₆ from (a209)₁₆ using 8's complement arithmetic.

solution

given numbers are,

minuend = a209

subtrahend = dc25

finding 15's complement of subtrahend,

15s complement of dc25 = ffff dc25 = 23da

adding minuend and 15's complement of subtrahend, we get,

a209 + 23da = c5e3

since, there is no end-around carry. the result is negative and is obtained by taking 15's complement of intermediate result, i.e.,

15s complement of c5e3 = ffff c5e3 = 3a1c

hence, the hexadecimal difference of a209 and dc25 us -3a1c.

subtraction using 16's complement

the 16's complement is also used to perform hexadecimal subtraction. the steps involved in hexadecimal subtraction using 16's complement is explained here −

step 1 − if a hexadecimal subtraction is defined as x y. then, find the 16's complement of subtrahend (y).
step 2 − add x and 16's complement of y.
step 3 − if there is an end-around carry, it indicates the result is positive and the final result is obtained by ignoring the end-around carry. if there is no end-around carry, the result is negative and is obtained by taking the 16's complement of the intermediate result and put a negative sign in front of it.

let us see some examples to understand the hexadecimal subtraction using 16's complement.

example 1

subtract (e7c)₁₆ from (f9d)₁₆ using 16's complement arithmetic.

solution

the given hexadecimal numbers are

minuend = f9d

subtrahend = e7c

taking 16's complement of the subtrahend, we get,

16s complement of e7c = (fff e7c) + 1 = 184

adding minuend and 16's complement of subtrahend, we get,

f9d + 184 = 1121

there is an end-around carry, indicating the result is positive. the final result is obtained ignoring the end-around carry.

hence, the hexadecimal difference of f9d and e7c is 121.

example 2

subtract (ff2)₁₆ from (ac5)₁₆ using 16's complement method.

solution

the given numbers are,

minuend = ac5

subtrahend = ff2

taking the 16's complement of the subtrahend, we get,

16s complement of ff2 = (fff ff2) + 1 = 00e

adding the minuend and 16's complement of subtrahend, we get,

ac5 + 00e = ad3

there is no end-around carry, indicating that the result is negative. the final result is obtained by taking the 16's complement of the intermediate result, as follows −

16s complement of ad3 = (fff ad3) + 1 = 52d

hence, the hexadecimal difference of ac5 and ff2 is -52d.

conclusion

in conclusion, complement arithmetic is a method used in digital electronics for simplifying subtraction operations. in this chapter, we explained the different types of complements and their application in subtraction operations along with solved examples.

binary codes are one of the important concepts in digital electronics. a binary code is a type of digital code consisting of two digits, 0 and 1. binary codes act as the primary language in any digital computing system. binary codes can represent different types of information such as numbers, letters, images, videos, etc.

in this chapter, we will explain the basics of binary codes, their working, advantages, limitations, and applications.

what are binary codes?

binary codes are used to represent text, numbers, images, or other types of information in the form of 0 and 1, i.e., binary digits. binary codes form the primary language of a digital computing system like a computer.

all digital system can understand and manipulate information expressed in binary language only. in the case of binary codes, each digit is called a binary digit or bit.

binary codes represents information using 0 and 1. in a digital system, the binary codes are organized into segments like bits or bytes. a bit is either a binary 0 or 1. when 8 bits are grouped together, then it is called a byte. each byte represents a piece of information in a digital system.

types of binary codes

binary codes can be classified into the following major types −

weighted binary codes
non-weighted binary codes
alphanumeric code
binary coded decimal (bcd)
error detecting code
error correction code

let us discuss each type of code in detail.

weighted binary codes

weighted binary codes are a type of binary code in which each bit position has a specific weight associated with its positional value.

in weighted binary codes, the positional weights are defined in terms powers of 2. the value of each bit depends on its position in the binary code. thus, in a given weighted binary code, the rightmost bit has the least weight and the leftmost bit has the highest weight.

in general, the weight of n^th bit in a weighted binary code is given by,

n^th bit = 2ⁿ

for example, let a 4-bit weighted binary code 1011. the value of the code is,

1 × 2³ + 0 × 2² + 1 × 2¹ + 1 × 2⁰

1 × 8 + 0 × 4 + 1 × 2 + 1 × 1

8 + 0 + 2 + 1 = 11

it is clear that the rightmost bit has a positional weight of 2⁰ = 1, whereas the leftmost bit has a positional weight of 2³ = 8.

examples of weighted binary codes are 8421 bcd code, 5211 code, 2421 code, etc.

non-weighted binary codes

in digital electronics, the type of digital or binary codes in which each bit position does not have a specific weight associated with it is known as a non-weighted binary code.

in non-weighted binary codes, the value of the bit does not depend on the position within the number. each bit position has an equal positional value.

examples of non-weighted binary codes include excess-3 code and gray code.

excess-3 code

excess-3 code is also called as xs-3 code. it is a type of non-weighted code used to express decimal numbers. excess-3 code words are derived from the 8421 bcd code words adding (0011)₂ or (3)₁₀ to each code word in 8421.

excess-3 codes are obtained as follows −

take a look at the following example −

gray code

gray codes are a type of non-weighted code. they are not arithmetic codes, which means there are no specific weights assigned to the bit position.

gray codes have a very special feature that, only one bit will change each time the decimal number is incremented (see the figure below). as only one bit changes at a time, gray codes are also known unit distance code.

gray codes are cyclic codes and they cannot be used in arithmetic operation.

gray codes are popularly used in shaft position encoders. a shaft position encoder produces a code word that represents the angular position of the shaft.

alphanumeric codes

a binary digit or bit can represent only two states '0' or '1'. but this is not enough for communication between two computers because there we need many more symbols for communication. these symbols are required to represent 26 alphabets with capital and small letters, numbers from 0 to 9, punctuation marks and other symbols.

alphanumeric codes are the codes that represent numbers and alphabetic characters. mostly such codes also represent other characters such as symbol and various instructions necessary for conveying information.

alphanumeric codes are binary codes that use character encoding schemes that represent both numbers and alphabetic characters. alphanumeric codes are mainly used in applications involving character representation and information exchange.

some common examples of alphanumeric codes are ascii (american standard code for information interchange), extended ascii, ebcdic (extended binary coded decimal interchange code), unicode, etc.

an alphanumeric code should at least represent 10 digits and 26 letters of the alphabet, i.e., total 36 items. the following three alphanumeric codes are very commonly used for data representation −

american standard code for information interchange (ascii)
extended binary coded decimal interchange code (ebcdic)
five bit baudot code

ascii code is a 7-bit code, whereas ebcdic is an 8-bit code. ascii code is more commonly used, while ebcdic is used primarily in large ibm computers.

binary coded decimal (bcd)

binary coded decimal or bcd is a binary code used to represent decimal numbers in their digital format. in this code, each decimal digit is represented by a 4-bit binary number. bcd is a way to express each of the decimal digits with a binary code. in bcd, each decimal digit is represented by a unique combination of binary bits.

bcd is mainly used in digital systems where decimal arithmetic operations are performed like in computers, calculators, display devices, digital sensors, etc.

in bcd, with 4 bits, we can represent sixteen numbers (0000 to 1111), but in bcd code only first ten of these are used (0000 to 1001). the remaining six code combinations, i.e., 1010 to 1111 are invalid in bcd.

advantages of bcd codes

bcd codes are very similar to the decimal system.
we need to remember the binary equivalent of the decimal numbers 0 to 9 only.

disadvantages of bcd codes

the addition and subtraction of bcd codes follow different rules.
bcd arithmetic is a little more complicated.
bcd needs more number of bits than binary to represent the decimal number. so, bcd is less efficient than binary.

error detecting codes

error detecting codes are special types of binary codes used to identify errors in digital communication and data storage. error detecting codes add redundancy to the data that allows receiver to identify if there is any error occurred. common examples of error detecting codes include parity bit, checksum, hamming code, etc.

error detecting codes are important to ensure integrity in data transmission and storage. they help in improving the reliability of the system.

what are errors?

an error is a condition when the output information does not match with the input information. during transmission, digital signals suffer from noise that can introduce errors in the binary bits travelling from one system to other. that means a 0 bit may change to 1 or a 1 bit may change to 0.

whenever a message is transmitted, it may get scrambled by noise or data may get corrupted. to avoid this, we use error-detecting codes which are additional data added to a given digital message to help us detect if an error occurred during transmission of the message. a simple example of error-detecting code is parity check.

error correcting codes

error correcting codes are binary codes designed to correct the errors occurred in a digital system during data transmission or storage. error correcting codes add some additional information to the data to be transmitted or stored.

error-correcting codes deploy the same strategy as error-detecting codes but additionally, such codes also detect the exact location of the corrupt bit. this allows the receiver to re-obtain the original data even if some of the bits are corrupted.

in error-correcting codes, parity check has a simple way to detect errors along with a sophisticated mechanism to determine the corrupt bit location. once the corrupt bit is located, its value is reverted (from 0 to 1 or 1 to 0) to get the original message.

just like error detecting codes, error correcting codes are important to maintain data integrity in digital communication and data storage applications.

different types of error correcting codes are used in different digital systems depending on the type of communication channel, error pattern, degree of error correction, etc. some common examples of error correcting codes are hamming code, reed-solomon code, low-density-parity-check code, bch code, etc.

how to detect and correct errors?

to detect and correct the errors, additional bits are added to the data bits at the time of transmission.

the additional bits are called parity bits. they allow detection or correction of the errors.
the data bits along with the parity bits form a code word.

parity checking of error detection

it is the simplest technique for detecting and correcting errors. the msb of an 8-bits word is used as the parity bit and the remaining 7 bits are used as data or message bits. the parity of 8-bits transmitted word can be either even parity or odd parity.

even parity − even parity means the number of 1's in the given word including the parity bit should be even (2,4,6,....).

odd parity − odd parity means the number of 1's in the given word including the parity bit should be odd (1,3,5,....).

use of parity bit

the parity bit can be set to "0" or "1" depending on the type of the parity required.

for even parity, this bit is set to 1 or 0 such that the number of "1 bits" in the entire word is even. see fig. (a).

for odd parity, this bit is set to 1 or 0 such that the number of "1 bits" in the entire word is odd. see fig. (b).

how does error detection take place?

parity checking at the receiver can detect the presence of an error if the parity of the receiver signal is different from the expected parity. that means, if it is known that the parity of the transmitted signal is always going to be "even" and if the received signal has an odd parity, then the receiver can conclude that the received signal is not correct.

if an error is detected, then the receiver will ignore the received byte and request for retransmission of the same byte to the transmitter.

advantages of binary codes

binary codes have several advantages in the field of digital electronics. here are the key benefits of using binary codes −

simplicity − binary codes use only two digits, i.e., 0 and 1 to represent information. it simplifies the electronic circuit design and implementation.
ease in implementation − binary codes use only two states namely, on and off. so, their implementation is straightforward.
ease of storage − binary codes are easy to store in digital memory devices like hard disk, cd, dvd, pen drive, etc. they require compact storage at higher efficiency.
easy and fast processing − binary codes can be efficiently processed using digital systems having an arithmetic and logic unit. they allow fast and error-free computing.
easy communication − binary codes provide an efficient method of information transmission at a very high speed. various error detecting and correcting techniques can be applied to binary codes that make the digital communication more efficient.
easy scalability − binary codes provide easy scalability of a digital system. we can increase the range of a digital system just by adding more bits in the code.
compatibility − binary codes are compatible with a wide range of digital devices and systems.
reliability − binary codes are highly immune to noise and interference that provide improved reliability in the digital system.

disadvantages of binary codes

binary codes have several advantages as given above. however, they also have some disadvantages and limitations.

some key disadvantages of binary codes are listed below −

binary codes are not human friendly. for human beings, reading and interpreting binary codes can be a complex task.
in some situations, binary codes have to be converted into other number systems that adds extra computational overhead to the system.
binary codes require higher transmission bandwidth in communication channel.
in binary codes, it is quite difficult to identify the errors. it becomes more challenging in case of long binary sequences.

applications of binary codes

binary codes are widely used in various fields of digital electronics due to their high efficiency in information representation.

listed below are some of the key applications of binary codes −

digital computers − binary codes are primarily used in digital computer to represent information and instructions.
digital communication − binary codes are also used for transmission of data and information using digital channels.
digital displays − binary codes are also used to display numbers and alphabets in digital systems.
barcode systems − binary codes are also used in barcode systems for product identification and inventory management. in this system, bars of different width and spaces between them represent binary digits that can be interpreted by a scanner.
data storage − binary codes are used to store information in digital devices like computer memory.
digital control systems − binary codes are used to program a digital control system. in a digital control system, binary codes are used to represent different types of control signals and instructions used for automation.
computer graphics − binary codes are also used in computer graphics to represent colors, shapes, pixel values, and other information.

conclusion

in conclusion, binary codes are one of the crucial components of a digital system. they are used to represent information and instructions in digital format. there are several different types of binary codes used in digital electronics.

different binary codes are used for different purposes depending on the nature of application. for example, ascii code is used for alphanumeric data representation. in this chapter, we explained the basic concepts of binary codes. in the upcoming chapters, we will explore the different types of binary codes and their applications in digital electronics.

the 8421 bcd code is one of the most commonly used binary codes in the field of digital electronics. this binary code is used to encode decimal digits from 0 to 9 in their equivalent binary format.

read this chapter to learn all about 8421 bcd codes including its advantages, limitations, and applications.

what is 8421 bcd code?

in digital electronics, the 8421 bcd code is a type of binary code. bcd stands for binary coded decimal. the 8421 bcd code is the most widely used binary code for expressing decimal numbers in their equivalent binary format.

the 8421 bcd code is also known as the natural bcd code. it is a binary code used to represent each decimal digit by using a unique combination of 4-bits. it is a weighted binary code and is also a sequential binary code.

the digits 8421 represents the weights assigned to each of the four bits, where the most significant bit has a weight of 8 and the least significant bit has a weight of 1.

in the 8421 bcd code, each decimal digit can be represented by a unique 4-bit binary code. the following table highlights the 8421 bcd code for each decimal digit.

decimal digit	8421 bcd code
0	0000
1	0001
2	0010
3	0011
4	0100
5	0101
6	0110
7	0111
8	1000
9	1001

the 8421 bcd code is the most commonly used code in digital electronics to represent decimal numbers in binary form. it is mainly used in digital devices where human machine interface is required.

advantages of 8421 bcd code

in digital electronics, the 8421 bcd code has several advantages, mainly in applications where decimal numbers are used in a digital system. some of the key benefits of the 8421 bcd code are given below −

the 8421 bcd code provides a natural way of representing decimal numbers. this is because, we can directly encode each decimal digit into its equivalent 4-bit binary number.
the 8421 bcd code allows for simple conversion between decimal and binary number systems. hence, it is quite useful in digital devices where human input is required.
the 8421 bcd code simplifies the arithmetic operations such as addition, subtraction, multiplication, and division of decimal numbers using a digital system like a calculator.
the 8421 bcd code is compatible with decimal displays. hence, it is commonly used in digital devices where the output has to be displayed on a decimal-based display like 7-segment display.

all these are the main advantages of 8421 bcd code. however, there are also some disadvantages of 8421 bcd code, lets discuss them.

disadvantages of 8421 bcd code

listed below are some of the major disadvantages of using the 8421 bcd code −

the 8421 bcd code is relatively less efficient than the pure binary code, as it requires a greater number of bits to represent a decimal number. for example, the decimal number 15 can be represented as 1111 in pure binary, whereas 0001 0101 in 8421 bcd.
the arithmetic operations such as addition, subtraction, multiplication, and division performed in 8421 bcd code are relative more complex than they are in pure binary.
the 8421 bcd code consumes more storage space as it uses 4 bits to represent each decimal digit.
in the case of 8421 bcd code arithmetic, the rules of binary arithmetic cannot be applied to the entire 8421 bcd number, but only to the individual groups of 4-bits.
the 8421 bcd codes are not suitable in applications where speed and efficiency are critical.
in 8421 bcd code, there are six illegal code combinations. they are 1010, 1011, 1100, 1101, 1110, and 1111.

thus, all these are the main disadvantages of the 8421 bcd code.

applications of 8421 bcd code

the 8421 bcd code is widely used in various applications in digital electronics. given below are some of the key applications of the 8421 bcd code −

the 8421 bcd code is mainly used in digital displays used in calculators, digital clocks and watches, etc. where decimal digits are to be displayed.

the 8421 bcd code is also used in device that accept numeric inputs like calculators.
in process control systems, the 8421 bcd code is used to represent and manipulate the decimal values.
the 8421 bcd codes are also used in embedded systems where human machine interaction is critical.
the 8421 bcd code is widely used in control panels of various electronic devices to display numerical values.

this is all about the basics of the 8421 bcd code. in the next section, we will explain how you can perform addition and subtraction of 8421 bcd codes.

addition in 8421 bcd code

the addition operations in 8421 bcd code are performed by individually adding the corresponding digits of the given decimal numbers expressed in 4-bit binary form.

in bcd addition, if there is no end-around carry, the sum is not an illegal bcd code. thus, it does not require any correction.

if there is an end-around carry from one group to the next group, of if the sum is an illegal code, then it is corrected by adding 0110 to the sum term and the resulting carry is added to the next group.

let us understand the bcd addition with the help of an example.

example

add 251 and 353 in the 8421 bcd code.

solution

converting the given decimal numbers into bcd code,

251 = 0010 0101 0001

353 = 0011 0101 0011

adding the bcd codes,

hence, the sum of 251 and 353 is 604.

subtraction in 8421 bcd code

to perform subtraction of decimal numbers using 8421 bcd code, we first convert the given decimal numbers into their 8421 bcd codes. then, we subtract the bcd subtrahend from the bcd minuend starting from the lsd.

if there is no borrow from the next higher group, then no correction is needed. if there is a borrow from the next higher group, then the result has to be obtained by subtracting 0110 from the intermediate difference term.

let us take an example to understand the bcd subtraction.

example

subtract 15 from 25 in 8421 bcd code.

solution

converting the given decimal number into bcd code,

25 = 0010 0101

15 = 0001 0101

subtracting the bcd code,

hence, the difference of 25 and 15 is 10.

conclusion

in conclusion, the 8421 bcd code is a natural binary coded decimal code widely used in digital electronics. it is primarily used in applications where decimal digits and human interaction are critical.

the most significant advantage of the 8421 bcd code is that it provides an easy conversion to and from decimal numbers. but it is less space efficient code because it requires more bits to represent a decimal digit.

excess-3 code is a non-weighted bcd (binary coded decimal) code. it is called excess-3 code because it is obtained by adding 0011 (3) to the 8421 bcd code. also called xs-3, the excess 3 code is a bcd code that represents each decimal digit as a 4-bit binary code.

the excess-3 binary code is a sequential code, so we can use it to perform arithmetic operations. also, it is a self-complementing code, therefore the subtraction operation by the complement method is simpler than that in the 8421 bcd code.

however, in the excess-3 code, there are six invalid codes, they are 0000, 0001, 0010, 1110, and 1111.

how to obtain excess-3 code?

we can obtain the excess-3 code by adding 0011 (3) to the natural 8421 bcd code. it is explained here −

decimal digit = 0
8421 bcd code = 0000
excess-3 code = 0000 + 0011 = 0011

decimal digit = 1
8421 bcd code = 0001
excess-3 code = 0001 + 0011 = 0100

similarly, we can obtain the excess-3 code for all the decimal digits.

the following table shows the excess-3 code for each decimal digit −

decimal digit	excess-3 code
0	0011
1	0100
2	0101
3	0110
4	0111
5	1000
6	1001
7	1010
8	1011
9	1100

note − the excess-3 code is not so widely used today. it was mainly used in early digital systems. nowadays, many other advanced and efficient binary codes are being used in place of the excess-3 code.

importance of excess-3 code in digital electronics

excess-3 code is one of the widely used binary codes in early digital systems. here are some of the key reasons why excess-3 code was used in the field of digital electronics −

it provides a simplified way of converting a decimal number into binary code.
it has self-complementing property that makes it suitable for error detection and correction applications.
it is sequential code, hence it can be used to perform arithmetic operations in digital systems.
excess-3 code is highly compatible with decimal io devices. thus, it provides a convenient interface between digital systems and other devices.

advantages of excess-3 code

although, the excess-3 code is less common in modern digital systems. but it has the following key benefits over other binary coding schemes −

excess-3 code provides an easy method of representing decimal numbers in binary form.
excess-3 code provides an easier way of performing addition and subtraction operations without using any complex conversion methods.
excess-3 code is quite easy to convert to and from decimal numbers.
excess-3 code being a binary-coded decimal is highly compatible with a wide range of decimal devices.

disadvantages of excess-3 code

excess-3 code has several advantages, but it also has certain disadvantages as well thats why it is less commonly used in modern digital systems. the following are some key disadvantages of excess-3 code −

excess-3 code is an inefficient binary representation of decimal numbers as compared to pure binary. this is because it requires more bits to represent a decimal digit.
excess-3 code requires additional arithmetic circuit to add 3 to the standard binary code.
excess-3 code has limited compatibility with pure binary systems.

applications of excess-3 code

excess-3 code was widely used in early digital systems and digital computers. the key areas of excess-3 code applications are listed below −

excess-3 code was used in early digital computers.
excess-3 code is also used in decimal data processing through digital systems.
excess-3 code is also used in digital devices likes printers, card readers, etc. where decimal data is employed.
the self-complementing property of excess-3 code makes it suitable to use in error detection and correction applications.
excess-3 code is also communication and data transmission applications.

excess-3 addition

in excess-3 addition, starting from lsd (least significant digit), we add the 4-bit group in each column.

if no end-around carry is generated from the addition of 4-bit group, we have to subtract 0011 from the sum term to obtain the result. this is because, no carry means the result is in xs-6 format. thus, we obtain the correct sum by adding 0011 to the sum term.

if an end-around carry is produced from the addition, we have to add 0011 to the sum term to obtain the corrected result. this is because the carry out represents that the sum term is an invalid excess-3 code, which is corrected by adding 0011 to the sum term.

let us understand the xs-3 addition with the help of examples.

example

add 35 and 28 in xs-3 code.

solution

the given decimal numbers and their xs-3 code are

35 = 0110 1000

28 = 0101 1011

adding the xs-3 codes,

hence, the correct sum of 35 and 28 is 1001 0110 in xs-3 and 63 in decimal.

excess-3 subtraction

in the xs-3 subtraction, starting from the least significant digit, we find the difference of two numbers by subtracting each group of 4-bits of subtrahend from he corresponding 4-bit group of the minuend.

in the xs-3 subtraction, if there is no borrow from the higher 4-bit group, then we add 0011 to the difference term to obtain the corrected result. this is because if there is no borrow, then the result is in the normal binary that has to be converted into xs-3 by adding 0011 to it.

if a borrow is taken from the next 4-bit group, then the difference term will be an invalid xs-3 code which is corrected by subtracting 0011 from it.

let us understand the xs-3 subtraction through a solved example.

example

subtract 28 from 56 in xs-3 code.

solution

given,

minuend = (56)₁₀ = (1000 1001)_xs-3

subtrahend = (28)₁₀ = (0101 1011)_xs-3

subtracting in the xs-3 code, we get,

hence, the corrected difference of the numbers 56 and 28 is 0101 1011 in xs-3 code and 28 in decimal.

conclusion

in conclusion, the excess-3 (xs-3) code is a binary coding scheme widely used in old digital systems. it is basically a bcd scheme used to represent decimal digits in binary format.

in modern digital systems, the excess-3 code is replaced by more efficient binary codes like 8421 bcd code, ascii code, etc.

the gray code is a type of reflective and unit distance binary code widely used in the field of digital electronics.

it is important to note that the gray code is not a binary coded decimal (bcd) code. thus, it cannot be used to directly represent a decimal number. it is also not a weighted code, therefore, we cannot use it to perform arithmetic operations.

in gray codes, the successive code words differ in one bit position only, hence it is a cyclic code or a unit distance code. the cyclic or reflective property of gray codes make it suitable to use in applications like error minimization in rotary encoders, communication systems, analog to digital converters, etc.

gray codes table

the following table shows 1-bit, 2-bit, 3-bit, and 4-bit gray codes and their reflective nature −

gray codes
1-bit	2-bit	3-bit	4-bit
0	00	000	0000
1	01	001	0001
	11	011	0011
	10	010	0010
		110	0110
		111	0111
		101	0101
		100	0100
			1100
			1101
			1111
			1110
			1010
			1011
			1001
			1000

importance of gray code

the gray code is one of the most popular reflective codes or unit distance codes. in digital electronics, it is important due to the following main reasons −

in gray code, only one-bit changes when moving from one word to the next i.e., two consecutive numbers differ in one bit only. this characteristic of the gray code minimizes the errors during transition.
the unit distance property of gray code allows it to use in rotary encoder for accurate position detection.
gray code reduces the errors significantly in analog to digital signal conversion.
gray code also helps to reduce the impact of signal noise in communication systems.
in data storage and transmission, gray code plays an important role in detecting and correcting errors.
in gray code, only bit changes at each transition. it is used to implement digital systems that consume less power.

overall, the gray code is an important type of reflective code in digital electronics and it is widely used in various digital electronic devices and systems.

advantages of gray code

in digital electronics, the gray code has several advantages over other types of binary codes. the following are some major benefits of gray code −

gray code minimizes the error during transition. this is because, it has two consecutive codes differ in one bit only.
gray code reduces the chances of errors in readings during position detection in rotary encoders.
in gray code, only one-bit changes at a time, this property eliminates the problem of technical glitch and electromagnetic interference.
in digital communication, the gray code can detect and correct errors, and hence improves the signal integrity.
being a unit distance code, the gray code provides a smooth transition from one state to the next.
in analog to digital conversion, gray code helps minimize the errors in sampling of analog signals.
gray code based digital systems consume less power than a system in which multiple bit changes simultaneously.

disadvantages of gray code

apart from advantages, gray code also has several disadvantages. some key disadvantages of gray codes are described below −

gray code involves more complex conversion process between binary and gray codes.
digital circuits that work with gray code are relatively more complex and expensive to design and implement.
gray code has limited natural ordering making it difficult to interpret by humans.
gray code is a non-weighted code. hence, it is not suitable to perform arithmetic operations.
gray code arithmetic is relatively more complex than other binary codes.
gray code is not suitable to use in general purpose digital computing systems.
gray code is not a universally adopted binary coding scheme due to some specific requirements of the applications.

applications of gray code

in digital electronics, gray code is used in several applications where reflective and unit distance properties are critical. the following are some main applications of gray code −

gray code is used in rotary encoders for accurate position detection.
gray code is also used in analog to digital converters for error-free sampling of analog signals.
gray codes are used in error detection and correction algorithms utilized in data storage and transmission systems.
gray code is used in digital circuits where smooth and sequential switching is desired.
gray code is used in digital devices like bar code scanners to encode information.
in the field robotics and automation, gray code is used to determine the position of robotic joints.
in electronic devices and systems, gray codes are used for sequential switching.

conclusion

in conclusion, gray code, also known as reflective code or unit distance code, is a non-weighted binary code used in different areas of digital electronics. gray code is not a universally adopted binary code, but it is mainly used in applications where the unit distance property is desired.

ascii stands for american standard code for information interchange. the ascii code is a popular coding scheme used in digital computing systems to encode characters.

in the ascii code, a unique integer value is assigned to each character like number, letter, symbol, etc. the standard ascii code defines a set of 128 characters, where each character can be represented by a unique 7-bit binary code. therefore, ascii code can represent total 2⁷ = 128 possible characters.

in digital electronics, the characters in ascii code are generally represented in decimal or hexadecimal notation. overall, the ascii code is a standard encoding scheme for representing characters in digital computers and communication systems.

properties of ascii code

the following are some key characteristics of ascii code −

ascii code assigns a unique numeric value to each character.
ascii code provides a way of representing letters, numbers, symbols, and control characters.
ascii code is compatible with a wide range of programming languages and digital devices.
ascii code supports various control characters for basic text formatting and device control.
ascii code has decimal and hexadecimal representation. hence, it is human-readable.
ascii code assigns numeric values to characters in a sequential order, making it an efficient encoding standard in terms of sorting and searching.
ascii code is highly space efficient and simple.

types of ascii code

ascii (american standard code for information interchange) code is basically a 7-bit character encoding standard used in digital electronics. but it is evolved with the advancement in computing technologies.

the following are two main types of ascii codes −

standard ascii code
extended ascii code

let's discuss the standard ascii codes first.

standard ascii code

it is a 7-bit character encoding standard having a range from 0 to 127 i.e., total 128 possible characters. it assigns a 7-bit unique binary code to each character including numbers, letters, symbols, and control characters.

the following table highlights the name, symbol and ascii code in decimal and binary form for the range from 0 to 127.

name	symbol	decimal	7-bit binary
null char	nul	0	00000000
start of heading	soh	1	00000001
start of text	stx	2	00000010
end of text	etx	3	00000011
end of transmission	eot	4	00000100
enquiry	enq	5	00000101
acknowledgment	ack	6	00000110
bell	bel	7	00000111
back space	bs	8	00001000
horizontal tab	ht	9	00001001
line feed	lf	10	00001010
vertical tab	vt	11	00001011
form feed	ff	12	00001100
carriage return	cr	13	00001101
shift out / x-on	so	14	00001110
shift in / x-off	si	15	00001111
data line escape	dle	16	00010000
device control 1 (oft. xon)	dc1	17	00010001
device control 2	dc2	18	00010010
device control 3 (oft. xoff)	dc3	19	00010011
device control 4	dc4	20	00010100
negative acknowledgement	nak	21	00010101
synchronous idle	syn	22	00010110
end of transmit block	etb	23	00010111
cancel	can	24	00011000
end of medium	em	25	00011001
substitute	sub	26	00011010
escape	esc	27	00011011
file separator	fs	28	00011100
group separator	gs	29	00011101
record separator	rs	30	00011110
unit separator	us	31	00011111
space		32	00100000
exclamation mark	!	33	00100001
double quotes	"	34	00100010
hash	#	35	00100011
dollar	$	36	00100100
percentage	%	37	00100101
ampersand	&	38	00100110
single quote	'	39	00100111
open parenthesis	(	40	00101000
close parenthesis	)	41	00101001
asterisk	*	42	00101010
plus	+	43	00101011
comma	,	44	00101100
hyphen	-	45	00101101
period, dot or full stop	.	46	00101110
slash or divide	/	47	00101111
zero	0	48	00110000
one	1	49	00110001
two	2	50	00110010
three	3	51	00110011
four	4	52	00110100
five	5	53	00110101
six	6	54	00110110
seven	7	55	00110111
eight	8	56	00111000
nine	9	57	00111001
colon	:	58	00111010
semicolon	;	59	00111011
less than	<	60	00111100
equals	=	61	00111101
greater than	>	62	00111110
question mark	?	63	00111111
at symbol	@	64	01000000
uppercase a	a	65	01000001
uppercase b	b	66	01000010
uppercase c	c	67	01000011
uppercase d	d	68	01000100
uppercase e	e	69	01000101
uppercase f	f	70	01000110
uppercase g	g	71	01000111
uppercase h	h	72	01001000
uppercase i	i	73	01001001
uppercase j	j	74	01001010
uppercase k	k	75	01001011
uppercase l	l	76	01001100
uppercase m	m	77	01001101
uppercase n	n	78	01001110
uppercase o	o	79	01001111
uppercase p	p	80	01010000
uppercase q	q	81	01010001
uppercase r	r	82	01010010
uppercase s	s	83	01010011
uppercase t	t	84	01010100
uppercase u	u	85	01010101
uppercase v	v	86	01010110
uppercase w	w	87	01010111
uppercase x	x	88	01011000
uppercase y	y	89	01011001
uppercase z	z	90	01011010
opening bracket	[	91	01011011
backslash	\	92	01011100
closing bracket	]	93	01011101
caret - circumflex	^	94	01011110
underscore	_	95	01011111
grave accent	`	96	01100000
lowercase a	a	97	01100001
lowercase b	b	98	01100010
lowercase c	c	99	01100011
lowercase d	d	100	01100100
lowercase e	e	101	01100101
lowercase f	f	102	01100110
lowercase g	g	103	01100111
lowercase h	h	104	01101000
lowercase i	i	105	01101001
lowercase j	j	106	01101010
lowercase k	k	107	01101011
lowercase l	l	108	01101100
lowercase m	m	109	01101101
lowercase n	n	110	01101110
lowercase o	o	111	01101111
lowercase p	p	112	01110000
lowercase q	q	113	01110001
lowercase r	r	114	01110010
lowercase s	s	115	01110011
lowercase t	t	116	01110100
lowercase u	u	117	01110101
lowercase v	v	118	01110110
lowercase w	w	119	01110111
lowercase x	x	120	01111000
lowercase y	y	121	01111001
lowercase z	z	122	01111010
opening brace	{	123	01111011
vertical bar	\|	124	01111100
closing brace	}	125	01111101
equivalency sign (tilde)	~	126	01111110
delete		127	01111111

extended ascii code

it is an 8-bit character encoding standard having a range from 0 to 255 i.e., total 256 possible characters. the extended ascii code adds extra 128 characters to the standard ascii code.

the following table shows the name, symbol and ascii code in decimal and binary form for the range from 128 to 255.

name	dec	bin
euro sign	128	10000000
	129	10000001
single low-9 quotation mark	130	10000010
latin small letter f with hook	131	10000011
double low-9 quotation mark	132	10000100
horizontal ellipsis	133	10000101
dagger	134	10000110
double dagger	135	10000111
modifier letter circumflex accent	136	10001000
per mille sign	137	10001001
latin capital letter s with caron	138	10001010
single left-pointing angle quotation	139	10001011
latin capital ligature oe	140	10001100
	141	10001101
latin capital letter z with caron	142	10001110
	143	10001111
	144	10010000
left single quotation mark	145	10010001
right single quotation mark	146	10010010
left double quotation mark	147	10010011
right double quotation mark	148	10010100
bullet	149	10010101
en dash	150	10010110
em dash	151	10010111
small tilde	152	10011000
trade mark sign	153	10011001
latin small letter s with caron	154	10011010
single right-pointing angle quotation mark	155	10011011
latin small ligature oe	156	10011100
	157	10011101
latin small letter z with caron	158	10011110
latin capital letter y with diaeresis	159	10011111
non-breaking space	160	10100000
inverted exclamation mark	161	10100001
cent sign	162	10100010
pound sign	163	10100011
currency sign	164	10100100
yen sign	165	10100101
pipe, broken vertical bar	166	10100110
section sign	167	10100111
spacing diaeresis - umlaut	168	10101000
copyright sign	169	10101001
feminine ordinal indicator	170	10101010
left double angle quotes	171	10101011
not sign	172	10101100
soft hyphen	173	10101101
registered trade mark sign	174	10101110
spacing macron - overline	175	10101111
degree sign	176	10110000
plus-or-minus sign	177	10110001
superscript two - squared	178	10110010
superscript three - cubed	179	10110011
acute accent - spacing acute	180	10110100
micro sign	181	10110101
pilcrow sign - paragraph sign	182	10110110
middle dot - georgian comma	183	10110111
spacing cedilla	184	10111000
superscript one	185	10111001
masculine ordinal indicator	186	10111010
right double angle quotes	187	10111011
fraction one quarter	188	10111100
fraction one half	189	10111101
fraction three quarters	190	10111110
inverted question mark	191	10111111
latin capital letter a with grave	192	11000000
latin capital letter a with acute	193	11000001
latin capital letter a with circumflex	194	11000010
latin capital letter a with tilde	195	11000011
latin capital letter a with diaeresis	196	11000100
latin capital letter a with ring above	197	11000101
latin capital letter ae	198	11000110
latin capital letter c with cedilla	199	11000111
latin capital letter e with grave	200	11001000
latin capital letter e with acute	201	11001001
latin capital letter e with circumflex	202	11001010
latin capital letter e with diaeresis	203	11001011
latin capital letter i with grave	204	11001100
latin capital letter i with acute	205	11001101
latin capital letter i with circumflex	206	11001110
latin capital letter i with diaeresis	207	11001111
latin capital letter eth	208	11010000
latin capital letter n with tilde	209	11010001
latin capital letter o with grave	210	11010010
latin capital letter o with acute	211	11010011
latin capital letter o with circumflex	212	11010100
latin capital letter o with tilde	213	11010101
latin capital letter o with diaeresis	214	11010110
multiplication sign	215	11010111
latin capital letter o with slash	216	11011000
latin capital letter u with grave	217	11011001
latin capital letter u with acute	218	11011010
latin capital letter u with circumflex	219	11011011
latin capital letter u with diaeresis	220	11011100
latin capital letter y with acute	221	11011101
latin capital letter thorn	222	11011110
latin small letter sharp s - ess-zed	223	11011111
latin small letter a with grave	224	11100000
latin small letter a with acute	225	11100001
latin small letter a with circumflex	226	11100010
latin small letter a with tilde	227	11100011
latin small letter a with diaeresis	228	11100100
latin small letter a with ring above	229	11100101
latin small letter ae	230	11100110
latin small letter c with cedilla	231	11100111
latin small letter e with grave	232	11101000
latin small letter e with acute	233	11101001
latin small letter e with circumflex	234	11101010
latin small letter e with diaeresis	235	11101011
latin small letter i with grave	236	11101100
latin small letter i with acute	237	11101101
latin small letter i with circumflex	238	11101110
latin small letter i with diaeresis	239	11101111
latin small letter eth	240	11110000
latin small letter n with tilde	241	11110001
latin small letter o with grave	242	11110010
latin small letter o with acute	243	11110011
latin small letter o with circumflex	244	11110100
latin small letter o with tilde	245	11110101
latin small letter o with diaeresis	246	11110110
division sign	247	11110111
latin small letter o with slash	248	11111000
latin small letter u with grave	249	11111001
latin small letter u with acute	250	11111010
latin small letter u with circumflex	251	11111011
latin small letter u with diaeresis	252	11111100
latin small letter y with acute	253	11111101
latin small letter thorn	254	11111110
latin small letter y with diaeresis	255	11111111

advantages of ascii code

the following are the key benefits of the ascii (american standard code for information interchange) code −

the ascii code provides a simple and straightforward encoding scheme to represent letters, numbers, and symbols.
ascii code is compatible with a wide range of programming languages and computing devices.
ascii code provides a compact character representation, where each character can be represented using 7-bits or 8-bits. hence, it is a space efficient encoding standard.
ascii code is a universally adopted encoding standard in the field of digital electronics.
ascii code has easy and simple implementation in hardware and software.

limitations of ascii code

ascii code has several advantages as described above, but it also has some limitations which are given below −

the standard ascii code has a limited set of 128 characters. this makes it unsuitable for representing characters of languages other than english.
the ascii code can be extended to 8-bits but it is not standardized beyond 7-bits.
ascii code is not suitable to use in systems that require a broad range of characters.

applications of ascii code

ascii code is a standard character encoding scheme used in wide range of applications in the field of digital electronics.

some major applications of ascii code are listed below −

ascii code is used in digital systems for textual communication.
ascii code is used in computer programming to represent alphanumeric data like letters, numbers, symbols, etc.
ascii code is also used in various communication protocols utilized for data transmission among devices.
in the field web technology, ascii code is used to represent different characters and symbols in a webpage.
ascii code is also used in database systems to represent text data.

conclusion

in conclusion, ascii (american standard code for information interchange) is a character encoding scheme widely used in digital systems. it is a 7-bit standard code used to represent a total of 128 characters including numbers, letters, symbols, and control characters.

the ebcdic (extended binary coded decimal interchange code) is an alphanumeric code used in digital systems to represent alphanumeric characters, such as letters, numbers, symbols, etc.

ebcdic is pronounced as "eb-si-dik". it is an 8-bit binary coded used for representing alphanumeric data in digital systems.

here, we will explain the ebcdic code in detail along with its advantages and applications.

what is ebcdic code?

ebcdic stands for extended binary coded decimal interchange code. it is an 8-bit binary code used in digital systems to represent alphanumeric data in digital form.

since, it is an 8-bit code, hence it can represent total 2⁸ = 256 possible characters. therefore, it is able to represent 128 more characters than standard ascii code, which is a 7-bit code.

the ebcdic code was developed by ibm (international business machine) and is mainly used in ibms mainframe computer systems. ebcdic code was primarily designed to be used in larger computers for alphanumeric data transmission.

although the ebcdic code can represent 256 characters, but some of the bit combinations in the ebcdic code are unassigned.

ebcdic code table

the following highlights the ebcdic code in their decimal and hexadecimal format −

the ebcdic code
decimal	hexadecimal	character	decimal	hexadecimal	character
0	00	nul	128	80
1	01	soh	129	81	a
2	02	stx	130	82	b
3	03	etx	131	83	c
4	04		132	84	d
5	05	ht	133	85	e
6	06		134	86	f
7	07	del	135	87	g
8	08		136	88	h
9	09		137	89	i
10	0a		138	8a
11	0b	vt	139	8b
12	0c	ff	140	8c
13	0d	cr	141	8d
14	0e	so	142	8e
15	0f	si	143	8f
16	10	dle	144	90
17	11		145	91	j
18	12		146	92	k
19	13		147	93	l
20	14		148	94	m
21	15		149	95	n
22	16	bs	150	96	o
23	17		151	97	p
24	18	can	152	98	q
25	19	em	153	99	r
26	1a		154	9a
27	1b		155	9b
28	1c	ifs	156	9c
29	1d	igs	157	9d
30	1e	irs	158	9e
31	1f	ius	159	9f
32	20		160	a0
33	21		161	a1	~
34	22		162	a2	s
35	23		163	a3	t
36	24		164	a4	u
37	25	lf	165	a5	v
38	26	etb	166	a6	w
39	27	esc	167	a7	x
40	28		168	a8	y
41	29		169	a9	z
42	2a		170	aa
43	2b		171	ab
44	2c		172	ac
45	2d	enq	173	ad
46	2e	ack	174	ae
47	2f	bel	175	af
48	30		176	b0
49	31		177	b1
50	32	syn	178	b2
51	33		179	b3
52	34		180	b4
53	35		181	b5
54	36		182	b6
55	37	eot	183	b7
56	38		184	b8
57	39		185	b9
58	3a		186	ba
59	3b		187	bb
60	3c		188	bc
61	3d	nak	189	bd
62	3e		190	be
63	3f	sub	191	bf
64	40	space	192	c0	{
65	41		193	c1	a
66	42		194	c2	b
67	43		195	c3	c
68	44		196	c4	d
69	45		197	c5	e
70	46		198	c6	f
71	47		199	c7	g
72	48		200	c8	h
73	49		201	c9	i
74	4a	[	202	ca
75	4b	.	203	cb
76	4c	<	204	cc
77	4d	(	205	cd
78	4e	+	206	ce
79	4f	\| !	207	cf
80	50	&	208	d0	}
81	51		209	d1	j
82	52		210	d2	k
83	53		211	d3	l
84	54		212	d4	m
85	55		213	d5	n
86	56		214	d6	o
87	57		215	d7	p
88	58		216	d8	q
89	59		217	d9	r
90	5a	! ]	218	da
91	5b	$	219	db
92	5c	*	220	dc
93	5d	)	221	dd
94	5e	;	222	de
95	5f	^	223	df
96	60	-	224	e0	\
97	61	/	225	e1
98	62		226	e2	s
99	63		227	e3	t
100	64		228	e4	u
101	65		229	e5	v
102	66		230	e6	w
103	67		231	e7	x
104	68		232	e8	y
105	69		233	e9	z
106	6a	\|	234	ea
107	6b	,	235	eb
108	6c	%	236	ec
109	6d	_	237	ed
110	6e	>	238	ee
111	6f	?	239	ef
112	70		240	f0	0
113	71		241	f1	1
114	72		242	f2	2
115	73		243	f3	3
116	74		244	f4	4
117	75		245	f5	5
118	76		246	f6	6
119	77		247	f7	7
120	78		248	f8	8
121	79		249	f9	9
122	7a	:	250	fa
123	7b	#	251	fb
124	7c	@	252	fc
125	7d		253	fd
126	7e	=	254	fe
127	7f	"	255	ff

characteristics of ebcdic code

the following are some key characteristics of the ebcdic code −

ebcdic code uses 8-bit binary coding scheme to represent alphanumeric data.
ebcdic code provides characters and symbols used in the field of commerce and finance. hence, it is well-suited for business data processing applications.
ebcdic code was primarily designed to use in ibm mainframe systems and it was compatible with punched card systems.
ebcdic code has a non-sequential binary assignment of characters.
ebcdic code is not directly compatible with ascii (american standard code for information interchange) due to its non-sequential binary assignment.
ebcdic code is a better choice for record-oriented processing in which the data is organized into fixed-length records like in batch processing.

limitations of ebcdic code

however, the ebcdic code has several advantages. but it also has some limitations as given below −

ebcdic code is not compatible with many modern computing systems that use ascii or unicode character encoding schemes.
ebcdic code has some unassigned binary patterns.
ebcdic code is less efficient character encoding standard in terms of storage utilization.
ebcdic code is not compatible with internet standards and protocols.

applications of ebcdic code

the ebcdic code is less common in modern computers and digital systems. but it has applications in some old digital systems. here are some key applications of ebcdic code −

ebcdic was mainly used in mainframe computers used in the field of finance and banking.
ebcdic code was also used in mainframe systems employed in government and healthcare sector.
ebcdic code is used in control systems used in manufacturing industries.
systems used for batch processing also use ebcdic code for data representation.

conclusion

ebcdic (extended binary coded decimal interchange code) is an 8-bit binary code used for digital representation of alphanumeric data such as letters, numbers, symbols, and control characters.

the ebcdic code was mainly designed for the mainframe systems developed by ibm for finance and banking sector. due to some limitations like incompatibility with ascii code, it is becoming less popular. in modern computing systems, the ebcdic code is not being used.

in digital electronics, we use different types of binary codes depending on the specifications of the digital systems. for proper data exchange among different digital systems, an essential process is carried out called code conversion.

code conversion is the process of converting a digital code from one format to another. code conversion is considered an essential process in various digital systems like computers, microcontrollers, communication systems, etc.

in this chapter, we will study the following major code conversions −

binary to bcd code conversion
bcd to binary code conversion
binary to gray code conversion
gray to binary code conversion
bcd to excess-3 code conversion
excess-3 to bcd code conversion
exces-3 to gray code conversion
gray to excess-3 code conversion

let us understand each type of code conversion in detail with the help of examples.

binary to bcd code conversion

bcd stands for binary coded decimal. hence, bcd is a decimal number represented in binary format. the conversion of pure binary into bcd is done as per the following steps −

step 1 − convert the given pure binary number into its equivalent decimal number.

step 2 − convert the obtained decimal number into bcd code.

let us understand the binary to bcd code conversion through an example.

example

convert (100111)₂ into bcd code.

solution

the given binary is,

binary = 100111

the decimal equivalent of given binary is

1 2⁵ + 0 2⁴ + 0 2³ + 1 2² + 1 2¹ + 1 2⁰

= 1 32 + 0 16 + 0 8 + 1 4 + 1 2 + 1 1

= 32 + 0 + 0 + 4 + 2 + 1 = (39)₁₀

now, converting (39)₁₀ into bcd code, we get,

(3)₁₀ = (0011)_bcd

(9)₁₀ = (1001)_bcd

thus, the bcd equivalent of the given binary number is,

(100111)₂ = (0011 1001)_bcd

bcd to binary code conversion

bcd to binary code conversion is the reverse process of binary to bcd code conversion as discussed previously.

the bcd to binary code conversion is performed as per the following steps −

step 1 − convert the given bcd code into its equivalent decimal format.

step 2 − convert the obtained decimal to the equivalent binary format.

the following example demonstrates the bcd to binary code conversion.

example

convert (1001 0111 0010)_bcd into binary code.

solution

converting the given bcd code into decimal equivalent −

(1001)_bcd = (9)₁₀

(0111)_bcd = (7)₁₀

(0010)_bcd = (2)₁₀

thus, the decimal equivalent of the given bcd is

(1001 0111 0010)_bcd = (972)₁₀

now, converting the obtained decimal to equivalent binary,

thus, the binary equivalent of (1001 0111 0010)_bcd is (1111001100)₂.

binary to gray code conversion

the process of converting a binary number into its equivalent gray code is termed as binary to gray code conversion. we know that the gray code is a binary coding scheme where two successive codes are differed in one bit only.

the step-by-step procedure to convert a binary code into gray code is explained below −

consider the given binary code is b_n b_n-1 b_n-2 b₂ b₁ and the equivalent gray code is g_n g_n-1 g_n-2 g₂ g₁. then,

step 1 − write the most significant bit (msb) or left most bit (b_n) of the binary code as the left most bit of the gray code (g_n), i.e.,

g_n = b_n

step 2 − xor the msb (b_n) and the next bit(b_n-1) of the binary code. record the result as the next bit of the gray code (g_n-1) i.e.,

$$\mathrm{g_{n-1} \: = \: b_{n} \oplus b_{n-1}}$$

step 3 − xor the next bits b_n-1 and b_n-2, record the result as the next bit of the gray code (g_n-2), i.e.,

$$\mathrm{g_{n-2} \: = \: b_{n-1} \oplus b_{n-2}}$$

step 4 − repeat this process until all the bits of the given binary code are exhausted. the obtained code will be the equivalent gray code.

let us understand the conversion of binary to gray code with the help of an example.

example

convert (110110)₂ into its equivalent gray code.

solution

the given binary code is,

binary = 110110

converting the given binary into its equivalent gray code,

hence, the equivalent gray code (101101)_gray

gray to binary code conversion

the process of translating a gray code into its equivalent binary code is called gray to binary code conversion. the conversion of a given gray code into the equivalent binary code is done as per the following steps −

consider the given gray code is g_n g_n-1 g_n-2 g₂ g₁ and the binary code is b_n b_n-1 b_n-2 b₂ b₁. then,

step 1 − the left most bit or msb of the equivalent binary code is same as the msb of the gray code, thus, copy it, i.e.,

b_n = g_n

step 2 − xor the msb of the binary number b_n and the next significant bit of the gray code (g_n-1). record it as the next significant bit of the binary number, i.e.,

$$\mathrm{b_{n-1} \: = \: b_{n} \oplus g_{n-1}}$$

step 3 − xor the bit b_n-1 and the next significant bit of the gray code (g_n-2). record the result as the next significant bit of the binary number, i.e.,

$$\mathrm{b_{n-2} \: = \: b_{n-1} \oplus g_{n-2}}$$

step 4 − continue this process until all the gray code bits are exhausted. the obtained sequence of bits will be the pure binary code equivalent of the given gray code.

let us take an example to understand the conversion of gray code to equivalent binary code.

example

convert the gray code (110010)_gray into its equivalent binary code.

solution

the conversion of gray code into binary is done as given below −

hence, the binary equivalent of (110010)_gray is (100011)₂.

bcd to excess-3 code conversion

the process of translating a given bcd (binary coded decimal) into its equivalent excess-3 code is referred to as bcd to excess-3 code conversion.

to convert a bcd code into its equivalent excess-3 code, we follow the steps given below −

step 1 − add 0011 (3) to each 4-bit group of given bcd code.

step 2 − the resulting code will be the equivalent xs-3 code.

it is important to note that in xs-3 code, there are six invalid bit combinations. they are 0000, 0001, 0010, 1101, 1110, and 1111.

let us take an example to understand the bcd to excess-3 code conversion.

example

convert (0011 1001 1000)_bcd into its equivalent xs-3 code.

solution

the conversion of given bcd code into its equivalent xs-3 code is shown below −

bcd code	0011	1001	1000
adding 0011	0011	0011	0011
xs-3 code	0110	1100	1011

thus, the equivalent xs-3 code of (0011 1001 1000)_bcd is (0110 1100 1011)_xs-3.

excess-3 to bcd code conversion

the process of converting a given xs-3 code into its equivalent bcd (binary coded decimal) code is known as excess-3 to bcd code conversion.

the conversion of excess-3 code into bcd code is done as per the following steps −

step 1 − subtract 0011 (3) from the each 4-bit group of xs-3 code.

step 2 − the resulting code will be the bcd code equivalent of the given xs-3 code.

let us understand the excess-3 to bcd code conversion with the help of an example.

example

convert (1100 1001 0110)_xs-3 into its equivalent bcd code.

solution

the conversion of xs-3 code to bcd code is given below −

xs-3 code	1100	1001	0110
subtracting 0011	0011	0011	0011
bcd code	1001	0110	0011

hence, the equivalent bcd code of (1100 1001 0110)_xs-3 is (1001 0110 0011)_bcd.

conclusion

in conclusion, code conversion is the process of converting a binary code from one format to another. for example, we can convert a bcd code into its equivalent pure binary code, or an xs-3 code into its equivalent bcd code, etc. in this chapter, we explained different types of code conversion.

we know that the bits 0 and 1 corresponding to two different range of analog voltages. so, during transmission of binary data from one system to the other, the noise may also be added. due to this, there may be errors in the received data at other system.

that means a bit 0 may change to 1 or a bit 1 may change to 0. we cant avoid the interference of noise. but, we can get back the original data first by detecting whether any error(s) present and then correcting those errors. for this purpose, we can use the following codes.

error detection codes
error correction codes

error detection codes

error detection codes are used to detect the error(s) present in the received data (bit stream). these codes contain some bit(s), which are included (appended) to the original bit stream. these codes detect the error, if it is occurred during transmission of the original data (bit stream).

example − parity code, hamming code.

error correction codes

error correction codes are used to correct the error(s) present in the received data (bit stream) so that, we will get the original data. error correction codes also use the similar strategy of error detection codes.

example − hamming code.

therefore, to detect and correct the errors, additional bit(s) are appended to the data bits at the time of transmission.

parity code

it is easy to include (append) one parity bit either to the left of msb or to the right of lsb of original bit stream. there are two types of parity codes, namely even parity code and odd parity code based on the type of parity being chosen.

even parity code

the value of even parity bit should be zero, if even number of ones present in the binary code. otherwise, it should be one. so that, even number of ones present in even parity code. even parity code contains the data bits and even parity bit.

the following table shows the even parity codes corresponding to each 3-bit binary code. here, the even parity bit is included to the right of lsb of binary code.

binary code	even parity bit	even parity code
000	0	0000
001	1	0011
010	1	0101
011	0	0110
100	1	1001
101	0	1010
110	0	1100
111	1	1111

here, the number of bits present in the even parity codes is 4. so, the possible even number of ones in these even parity codes are 0, 2 & 4.

if the other system receives one of these even parity codes, then there is no error in the received data. the bits other than even parity bit are same as that of binary code.
if the other system receives other than even parity codes, then there will be an error(s) in the received data. in this case, we cant predict the original binary code because we dont know the bit position(s) of error.

therefore, even parity bit is useful only for detection of error in the received parity code. but, it is not sufficient to correct the error.

odd parity code

the value of odd parity bit should be zero, if odd number of ones present in the binary code. otherwise, it should be one. so that, odd number of ones present in odd parity code. odd parity code contains the data bits and odd parity bit.

the following table shows the odd parity codes corresponding to each 3-bit binary code. here, the odd parity bit is included to the right of lsb of binary code.

binary code	odd parity bit	odd parity code
000	1	0001
001	0	0010
010	0	0100
011	1	0111
100	0	1000
101	1	1011
110	1	1101
111	0	1110

here, the number of bits present in the odd parity codes is 4. so, the possible odd number of ones in these odd parity codes are 1 & 3.

if the other system receives one of these odd parity codes, then there is no error in the received data. the bits other than odd parity bit are same as that of binary code.
if the other system receives other than odd parity codes, then there is an error(s) in the received data. in this case, we cant predict the original binary code because we dont know the bit position(s) of error.

therefore, odd parity bit is useful only for detection of error in the received parity code. but, it is not sufficient to correct the error.

hamming code

hamming code is useful for both detection and correction of error present in the received data. this code uses multiple parity bits and we have to place these parity bits in the positions of powers of 2.

the minimum value of 'k' for which the following relation is correct (valid) is nothing but the required number of parity bits.

$$\mathrm{2^{k} \: \geq \: n \: + \: k \: + \: 1}$$

where,

'n' is the number of bits in the binary code (information)

'k' is the number of parity bits

therefore, the number of bits in the hamming code is equal to n + k.

let the hamming code is $\mathrm{b_{n+k}b_{n+k-1} \: ..... \: b_{3}b_{2}b_{1}}$ & parity bits $\mathrm{p_{k}, \: p_{k-1}, \: .... \: p_{1}}$. we can place the 'k' parity bits in powers of 2 positions only. in remaining bit positions, we can place the n bits of binary code.

based on requirement, we can use either even parity or odd parity while forming a hamming code. but, the same parity technique should be used in order to find whether any error present in the received data.

follow this procedure for finding parity bits.

find the value of p₁, based on the number of ones present in bit positions b₃, b₅, b₇ and so on. all these bit positions (suffixes) in their equivalent binary have 1 in the place value of 2⁰.
find the value of p₂, based on the number of ones present in bit positions b₃, b₆, b₇ and so on. all these bit positions (suffixes) in their equivalent binary have 1 in the place value of 2¹.
find the value of p₃, based on the number of ones present in bit positions b₅, b₆, b₇ and so on. all these bit positions (suffixes) in their equivalent binary have 1 in the place value of 2².
similarly, find other values of parity bits.

follow this procedure for finding check bits.

find the value of c₁, based on the number of ones present in bit positions b₁, b₃, b₅, b₇ and so on. all these bit positions (suffixes) in their equivalent binary have 1 in the place value of 2⁰.
find the value of c₂, based on the number of ones present in bit positions b₂, b₃, b₆, b₇ and so on. all these bit positions (suffixes) in their equivalent binary have 1 in the place value of 2¹.
find the value of c₃, based on the number of ones present in bit positions b₄, b₅, b₆, b₇ and so on. all these bit positions (suffixes) in their equivalent binary have 1 in the place value of 2².
similarly, find other values of check bits.

the decimal equivalent of the check bits in the received data gives the value of bit position, where the error is present. just complement the value present in that bit position. therefore, we will get the original binary code after removing parity bits.

example 1

let us find the hamming code for binary code, d₄d₃d₂d₁ = 1000. consider even parity bits.

the number of bits in the given binary code is n=4.

we can find the required number of parity bits by using the following mathematical relation.

$$\mathrm{2^{k} \: \geq \: n \: + \: k \: + \: 1}$$

substitute, n=4 in the above mathematical relation.

$$\mathrm{\rightarrow \: 2^{k} \: \geq \: 4+k+1}$$

$$\mathrm{\rightarrow \: 2^{k} \: \geq \: 5+k}$$

the minimum value of k that satisfied the above relation is 3. hence, we require 3 parity bits p₁, p₂, and p₃. therefore, the number of bits in hamming code will be 7, since there are 4 bits in binary code and 3 parity bits. we have to place the parity bits and bits of binary code in the hamming code as shown below.

the 7-bit hamming code is −

$$\mathrm{b_{7}b_{6}b_{5}b_{4}b_{3}b_{2}b_{1} \: = \: d_{4}d_{3}d_{2}p_{3}d_{1}p_{2}bp_{1}}$$

by substituting the bits of binary code, the hamming code will be

$$\mathrm{b_{7}b_{6}b_{5}b_{4}b_{3}b_{2}b_{1} \: = \: 100p_{3}op_{2}p_{1}}$$

now, let us find the parity bits.

$$\mathrm{p_{1} \: = \: b_{7} \: \oplus \: b_{5} \: \oplus \: b_{3} \: = \: 1 \: \oplus \: 0 \: \oplus \: 0 \: = \: 1}$$

$$\mathrm{p_{2} \: = \: b_{7} \: \oplus \: b_{6} \: \oplus \: b_{3} \: = \: 1 \: \oplus \: 0 \: \oplus \: 0 \: = \: 1}$$

$$\mathrm{p_{3} \: = \: b_{7} \: \oplus \: b_{6} \: \oplus \: b_{5} \: = \: 1 \: \oplus \: 0 \: \oplus \: 0 \: = \: 1}$$

by substituting these parity bits, the hamming code will be −

$$\mathrm{b_{7}b_{6}b_{5}b_{4}b_{3}b_{2}b_{1} \: = \: 1001011}$$

example 2

in the above example, we got the hamming code as −

$$\mathrm{b_{7}b_{6}b_{5}b_{4}b_{3}b_{2}b_{1}= 1001011}$$.

now, let us find the error position when the code received is −

$$\mathrm{b_{7}b_{6}b_{5}b_{4}b_{3}b_{2}b_{1}= 1001111}$$

now, let us find the check bits.

$$\mathrm{c_{1} \: = \: b_{7} \: \oplus \: b_{5} \: \oplus \: b_{3} \: \oplus \: b_{1} \: = \: 1 \: \oplus \: 0 \: \oplus \: 1 \: \oplus1 \: = \: 1}$$

$$\mathrm{c_{2} \: = \: b_{7} \: \oplus \: b_{6} \: \oplus \: b_{3} \: \oplus \: b_{2} \: = \: 1 \: \oplus \: 0 \: \oplus \: 1 \: \oplus \: 1 \: = \: 1}$$

$$\mathrm{c_{3} \: = \: b_{7} \: \oplus \: b_{6} \: \oplus \: b_{5} \: \oplus \: b_{4} \: = \: 1 \: \oplus \: 0 \: \oplus \: 0 \: \oplus \: 1 \: = \: 0}$$

the decimal value of check bits gives the position of error in received hamming code.

$$\mathrm{c_{3}c_{2}c_{1} \: = \: \left ( 011 \right )_{2} \: = \: \left ( 3 \right )_{10}}$$

therefore, the error present in third bit (b₃) of hamming code. just complement the value present in that bit and remove parity bits in order to get the original binary code.

in digital electronics, a logic gate is the most elementary component of a digital circuit or a digital system. in this chapter, we will learn the basics of logic gates, their advantages, limitations, and applications. so, lets get started with the basic definition of a "logic gate".

what is a logic gate?

a logic gate is an electronic circuit that performs logical operations based on the inputs provided to it and produces a logical output that can be either "true" or "false".

logic gates are the primary building blocks of all digital circuits and systems. the operation of logic gates is based on the boolean mathematics.

types of logic gates

logic gates can be broadly classified into the following three categories −

basic logic gates − and gate, or gate, not gate
universal logic gates − nand gate and nor gate
derived logic gates − xor gate and xnor gate

all these gates are combined together to implement complex practical digital systems to perform various computational and logical operations.

working principle of logic gates

the working of logic gates is based on the laws of boolean algebra. in boolean algebra, the binary variables and logical operators are used to perform operations.

a boolean variable can have one of the two possible values, i.e., 0 or 1. where, 0 represents "false" or "low state" while 1 represents "true" or "high state".

the operation of each logic gate is described using a table of input and output variables, which is called truth table of the logic gate.

a logic gate produces a specific output depending on the relationship described in its truth table. hence, boolean algebra forms the foundation of working of logic gates.

major components of logic gates

a logic gate consists of several electronic components, some of which are listed here −

transistor

transistors are the main electronic components used to design a logic gate circuit. a number of transistors are connected together to form a circuit that can perform different logic gate functions.

input terminals

a logic gate can have one or more input terminals. each input terminal can receive binary signals.

output terminals

logic gates have an output terminal that produces the result of the logical operation performed by the logic gate.

power supply

being an electronic circuit, a logic gate requires a source of electric power to work. in general, a voltage vcc represents the power supply.

ground terminal

the ground terminal is a 0 v terminal. it acts as a reference point in the circuitry of the logic gate.

connecting wires

these are essential components in the logic gate circuitry. the connecting wires are required to connect transistors and other components of a logic gate in a circuit.

these are the main components of a logic gate essentially required to design and implement it. however, some advanced logic gates can have some more circuit components as well.

advantages of logic gates

logic gates play an important role in the field of digital electronics. logic gates have numerous advantages due to which they are widely used in various applications.

some of the major advantages of logic gates are given below −

logic gates can process digital signals which are essential component in modern computing systems.
logic gates can perform logical or boolean operations efficiently.
being digital circuits, logic gates are highly immune to noise and electromagnetic interference. hence, they are more reliable.
multiple logic gates can be combined to obtain higher order logic gates and design complex digital systems.
logic gates are versatile in terms of logical operations, as they can perform a variety of operations when configured in different ways.
logic gates have high operating speed.
logic gates consume lower amount of electric power. hence, they result in higher energy efficiency.
logic gates can be integrated in the form ics. this feature enables engineers to design compact and efficient electronic devices.

all these advantages make logic gates the essential components in the field of digital electronics.

limitations of logic gates

logic gates have several advantages, but they also have some limitations and drawbacks.

the main limitations of logic gates are described below −

logic gates have a finite propagation delay and take a certain amount of time to process. this can be a limiting factor in case of high-speed digital systems.
in some complex digital systems, logic gates can degrade the quality of the signals.
logic gates can operate with binary voltage levels only.
in large digital circuits, the use of multiple logic gates can increase complexity of the circuit.
the continuous switching i.e., toggle between on and off states can heat up the logic gates and degrade their performance.
design, fabrication, and testing of logic gate is a complex and cost intensive process.
logic gates require addition analog to digital converts to process analog signals.
logic gates are highly sensitive faults and errors.

applications of logic gates

as we already discussed that logic gates are the primary building blocks of all digital circuits and systems. hence, they are used in a wide range of applications in digital electronics. the following are some key applications of the logic gates −

logic gates are used in digital computers to perform arithmetic, logical, and control functions.
in memory devices, logic gates are used to implement memory cells to store digital data in the form of bits.
logic gates are used in manufacturing microprocessors and microcontrollers.
in systems used in the digital signal processing, the logic gates play an important role to perform various operations such as modulation, filtering, algorithm execution, etc.
logic gates are also used in digital communication systems to perform functions like encoding, decoding, signal processing, etc.
in control systems, logic gates are used to manage and control the operations of machinery.
logic gates are also used to implement automated operation of security systems.

conclusion

in conclusion, a logic gate is an electronic circuit that works on the principle of boolean algebra and performs various logical operations.

logic gates are the fundamental building blocks of digital electronic systems. they are widely used in digital systems to perform operations such as controlling, processing, manipulation of digital data, etc.

in this chapter, we explained the basic concepts of logic gates and their applications. in the next chapters, we will discuss about different types of logic gates such as or, and, not, nor, nand, etc. in detail.

in digital electronics, there are several different types of logic gates such as and gate, or gate, not gate, etc. in this chapter, we will explain the theory of and gate.

an and gate is a basic logic gate used to implement various complex digital circuits and systems. the and gate performs the logical multiplication of inputs applied to it and produces an output accordingly.

what is an and gate?

an and gate is a type of basic logic gate used in various digital circuits and systems. it produces a high or logic 1 or true output, only when all its inputs are high or logic 1 or true. for all other combinations of inputs, it produces a low or logic 0 or false output.

the logic symbols for the two and three input and gates are depicted in the following figure.

here, a, b, and c are the input variables and y is the output variable.

in this chapter, we will cover and gates having three inputs only. but we can design an and gate for any number of input variables.

truth table of and gate

the truth table of an and gate contains inputs and outputs, and specifies the relationship between them.

the truth table of a two-input and gate is given below −

input		output
a	b	y
0	0	0
0	1	0
1	0	0
1	1	1

from this truth table of two-input and gate, it can be observed that the output of the and gate is logic 1 or high, only when both inputs are logic 1 or high.

the following table represents the truth table of a three-input and gate −

input			output
a	b	c	y
0	0	0	0
0	0	1	0
0	1	0	0
0	1	1	0
1	0	0	0
1	0	1	0
1	1	0	0
1	1	1	1

this truth table shows that the output is high or logic 1 only when all the three inputs to the and gate are high or logic 1. for rest input combinations, the output is low or logic 0.

from these truth tables of and gate, we can conclude that an and gate produces a high or logic 1 output, only when all its inputs are high or logic 1, otherwise the output is low or logic 0.

working of and gate

the working of a two-input and gate is explained below −

if a = 0 and b = 0, the output is low i.e., y = 0.
if a = 0 and b = 1, the output is low i.e., y = 0.
if a = 1 and b = 0, the output is low i.e., y = 0.
if a = 1 and b = 1, the output is high i.e., y = 1.

the working of a three-input and gate is explained below −

if a = 0, b = 0, and c = 0, the output is low i.e., y = 0.
if a = 0, b = 0, and c = 1, the output is low i.e., y = 0.
if a = 0, b = 1, and c = 0, the output is low i.e., y = 0.
if a = 0, b = 1, and c = 1, the output is low i.e., y = 0.
if a = 1, b = 0, and c = 0, the output is low i.e., y = 0.
if a = 1, b = 0, and c = 1, the output is low i.e., y = 0.
if a = 1, b = 1, and c = 0, the output is low i.e., y = 0.
if a = 1, b = 1, and c = 1, the output is high i.e., y = 1.

this is all about working of a two-input and a three-input and gates.

boolean expression of and gate

boolean expression is a logic equation or a logic function that represents the mathematical relationship between inputs and output of the and gate.

the boolean expression of a two-input and gate is given by,

y = a · b

where, a and b are inputs and y is the output. this expression is read as "y is equal to a and b." the dot (·) symbol represents the and operation.

for the three-input and gate, the boolean expression is given by,

y = a · b · c

it is read as "y is equal to a and b and c".

in the same way, we can obtain the boolean expression for an and gate having any number of input variables.

and gate using transistor

the transistor circuit of a two-input and gate is shown in the following figure.

the implementation of and gate using transistors requires as many transistors as the number of inputs. for example, a two-input and gate requires two transistors.

working of transistor and gate

the working the transistor and gate shown in the above figure is explained below −

when both inputs a and b are low, the transistors q₁ and q₂ remain in off state and act as open switch. therefore, the output line y will directly connect to the ground potential. thus, the output is low or logic 0.

when the input a is low and the input b is high, the first transistor q₁ is off and the second transistor q₂ is on. but still the supply voltage will not connect to the output line and the output line will remain at ground potential. consequently, the output is low or logic 0.

when the input a is high and the input b is low, the transistor q₁ will conduct and the transistor q₂ will remain off. in this condition, the output line does not receive the supply voltage but connect to the ground potential. hence, for this input combination, the output is low or logic 0.

when both inputs a and b are high, both transistors q₁ and q₂ will turn on and act as closed switches. in this condition, the supply voltage directly connect to the output line. this makes output of the circuit high or logic 1.

this is how the above transistor circuit acts a two-input and gate. we can add more transistors to implement a high order and gate.

and gate using switches

we can also implement and gate logic using a battery, switches, and a lamp or bulb. the following figure shows the and gate using switches.

in this and gate circuit, we have a voltage source, two switches representing two input terminals of the and gate, and a lamp representing the output.

from the circuit, we see that if both switches a and b are closed, there will be a closed for current to flow in the circuit. hence, the lamp will glow that represents the high or logic 1 output.

if both or any of the two switches be open, there will be a break in the current path, making the lamp off. this represents the low or logic 0 state of the output of the and gate.

this way, the above depicted switching circuit performs the and gate operation. by adding more number of switches in series, we can implement a higher order and gate.

and gate ic

in practice, there is an integrated circuit namely, ic 7408 which is a most commonly used and gate ic. this and gate ic is implemented in transistor-transistor logic (ttl). the block diagram of the and gate ic 7408 is shown in the following figure.

it is a quad-2 and gate ic having four two-input and gates integrated on a single chip. it has 14 pins.

conclusion

in conclusion, the and gate is a fundamental logic gate used in digital circuits to implement the boolean multiplication function.

the output of the and gate is high or logic 1 only when all its inputs are high or logic 1. otherwise, it generates a low or logic 0 output.

and gate plays an important role in various digital electronic applications such as data processing, memory devices, arithmetic logic units, control systems, and more.

in digital electronics, an or gate is a basic logic gate having two or more input lines and one output line. it performs the boolean addition function.

in this chapter, we will explain the theory of the or gate. here, we will cover the definition of or gate, its logic symbol, boolean expression, truth table, operation, and circuits.

so, lets get started with the basic definition of or gate.

what is an or gate?

an or gate is a type of logic gate used to perform logical addition. it can have two or more inputs and one output.

the output of the or gate is low or logic 0 only when all its inputs are low or logic 0. for rest input combinations, the output of the or gate is high or logic 1.

the logic symbols for a two-input and a three-input or gate are shown in the following figure.

here, a, b, and c are the input lines and y is the output line.

truth table of or gate

the truth table is a table that shows the relationship between different input combinations and output.

the following is the truth table for a two-input or gate −

input		output
a	b	y
0	0	0
0	1	1
1	0	1
1	1	1

the following table shows the truth table for a three-input or gate −

input			output
a	b	c	y
0	0	0	0
0	0	1	1
0	1	0	1
0	1	1	1
1	0	0	1
1	0	1	1
1	1	0	1
1	1	1	1

from these two truth tables, we can observe that the output of the or gate is logic 0 or low, only when all the inputs to the or gate are logic 0 or low. otherwise, the output of the or gate is high or logic 1.

boolean expression of or gate

the boolean expression is a logical function that describes the mathematical relationship between inputs and output of the or gate.

the boolean expression of a two-input or gate is given below −

y = a + b

here, a and b are input variables and y is the output variable. this expression is read as "y is equal to a or b". here, the "+" sign represents the or operation.

similarly, the boolean expression of a three-input or gate is given below −

y = a + b + c

here, a, b, and c are the inputs and y is the output.

in the same way, we can extend this expression to any number of input variables.

working of or gate

the operation of a two input or gate for different input combinations is described below −

if a = 0 and b = 0, the output of the or gate is y = 0.
if a = 0 and b = 1, the output of the or gate is y = 1.
if a = 1 and b = 0, the output of the or gate is y = 1.
if a = 1 and b = 1, the output of the or gate is y = 1.

this theory explains that when both inputs applied to an or gate are low or logic 0, the output of the or gate is also low or logic 0, otherwise it is high or logic 1.

similarly, the working of a three-input or gate is described below −

if a = 0, b = 0, and c = 0, the output of the or gate is y = 0.
if a = 0, b = 0, and c = 1, the output of the or gate is y = 1.
if a = 0, b = 1, and c = 0, the output of the or gate is y = 1.
if a = 0, b = 1, and c = 1, the output of the or gate is y = 1.
if a = 1, b = 0, and c = 0, the output of the or gate is y = 1.
if a = 1, b = 0, and c = 1, the output of the or gate is y = 1.
if a = 1, b = 1, and c = 0, the output of the or gate is y = 1.
if a = 1, b = 1, and c = 1, the output of the or gate is y = 1.

this theory also explains that the output of an or gate is low or logic 0, only when all the three inputs are low or logic 0.

or gate using transistors

we can implement the or gate logic circuit using transistors. the implementation of a two-input or gate using bjt transistors is shown in the following figure.

this or gate circuit is also referred to as transistor-transistor logic (ttl) or gate.

working of transistor or gate

the operation of the above shown transistor or gate circuit is explained below −

when both inputs a and b are low, i.e., both a and b are connected to a low voltage (0 v), the transistors q₁ and q₂ remain off and act as open switches. the result is that the output line will directly connect to the ground potential. this makes the output of the circuit low or logic 0.

if the input a is low and the input b is high, the transistor q₁ will be off, and the transistor q₂ will turn on and acts as a closed switch. thus, the supply voltage v_cc will connect to the output line through the transistor q₂. consequently, the output of the circuit is high or logic 1.

if the input a is high and the input b is low, the transistor q₁ will conduct, while the transistor q₂ will act as open switch. thus, the output line will connect to the power supply v_cc through the transistor q₁. consequently, the output of the circuit is high or logic 1.

when both inputs a and b are high, both transistor q₁ and q₂ will conduct and act as the closed switches. the output line will connect to the power supply v_cc through both transistors, this makes the output of the circuit high or logic 1.

this theory explains that when both inputs of the circuit are connected to logic 0 or low signal, the output is low or logic 0, otherwise the output is high or logic 1. hence, this circuit implements the or gate function.

we can add more transistors to the circuit to implement a higher order or gate.

or gate using switches

we can also use electrical switches, a battery, and a lamp to implement the or logic operation. the following figure depicts the switching circuit diagram of a two-input or gate.

the working of this circuit is explained below −

when both switches a and b are open, there is closed path for the flow of current. hence, the lamp will remain off which represents the low or logic 0 output.

if the switch a is open and the switch b is closed, there is a closed path for the current flow through the switch b. in this case, the lamp will glow and represents the high or logic 1 output.

if the switch a is closed and the switch b is open, there will be a closed path for the current to flow through the switch a. in this case, the lamp will glow that represents the high or logic 1 output.

if both switches a and b are closed, there will a closed path for the current to flow. this will also turn on the lamp and represents the high or logic 1 output.

this way, the above shown switching circuit implements the or gate operation. we can add more switches in parallel to implement a higher order or gate logic.

or gate ic

in practice, the or gate is available in the form of integrated circuits or ics. the most popular or gate ic is ic 7432 which is a quad 2-input or gate ic. it has four two-input or gates.

the following figure depicts the pin and block diagram of the or gate ic 7432.

the or gate ic 7432 has 14 pins and it is a transistor-transistor logic (ttl) or gate ic.

conclusion

in conclusion, the or gate is a basic logic gate having two or more input lines and one output line. it produces a low or logic 0 output only when all its inputs are low, otherwise it produces a high or logic 1 output.

in this chapter, we explained the theory of or gate. here, we covered only two and three-input or gates. but the same theoretical and technical explanation is valid for or gate with any number of inputs.

the not gate is a type of basic logic gate having only one input line and one output line. it performs the inversion operation.

in this chapter, we will explain the theory of not gate, its logic symbol, working, truth table, boolean expression, etc.

in digital electronics, the not gate is used as the basic building block of complex digital systems.

what is a not gate?

the not gate is a type of basic logic gate used in digital electronics to implement the inversion function. since it performs the inversion operation, it is also known as inverter.

it has only one input line and one output line. the output of the not gate is high or logic 1 when its input is low or logic 0. the output of the not gate is low or logic 0 when its input is high or logic 1.

the logic symbol of the not gate is shown in the following figure −

here, a is the input line and y is the output line of the not gate.

truth table of not gate

the truth table of not gate is a table of input and output that represent the relationship between them. here is the truth table of the not gate −

input (a)	output (y)
0	1
1	0

from this truth table, we can observe that the not gate inverts the input applied to it. hence, if we apply a high input, it produces a low output and vice-versa.

boolean expression of not gate

the boolean expression of the not gate is a logical function that explains the relationship between input and output of the not gate mathematically.

the boolean expression of the not gate is given below −

$$\mathrm{y \: = \: \bar{a} \: = \: a'}$$

here, the symbols "(-) overbar" and "(') prime" represents the inversion or complement operation.

this expression is read as "y is equal to a bar or a prime or noted a".

working of not gate

the not gate performs the inversion operation of the input applied. the complete working of the not gate for possible input combinations is explained below −

if a = 0, the output is y = 1.
if a = 1, the output is y = 0.

thus, the output of the not gate is the complement of the input applied to it.

not gate using transistor

we can implement the not gate logic by using a bjt transistor. when the not gate is implemented using a transistor, it is called a transistor inverter.

the following figure shows the circuit diagram of a not gate using transistor or transistor inverter.

working of transistor not gate

the above transistor inverter circuit operates as described below −

when the input a is low, the transistor will be inactive and acts as an open switch. thus, there is no closed path between the power supply v_cc and ground terminal. hence, the total supply voltage will appear at the output line. this represents the high or logic 1 output.

when the input a is high, the transistor will turn on and act as a closed switch. as a result, the power supply is directly connected to the ground terminal and the voltage available at the output line is equal to the ground voltage. this makes the output of the circuit low or logic 0.

this is how, the above transistor circuit implements the not logic.

not gate using switches

we can also implement the not gate operation using a battery, a switch, and a lamp. the circuit diagram for the not gate using switches is shown in the following figure.

in this circuit, when the switch a is open, i.e., logic 0, the current follows the path through the lamp making it glow. this represents a high or logic 1 output.

if the switch a is closed, i.e., logic 1, the current flows through the short-circuited path provided by the closed switch and no current will flow through the lamp. hence, in this case, the lamp will be off and represents the low or logic 0 output.

from this discussion, it is clear that the output is high when the input is low and vice-versa. thus, the above switching circuit implements the not gate logic.

not gate ic

the not gate comes in the form of integrated circuits or ics. the most commonly used not gate ic is ic 7404. it contains six tl (transistor logic) not gates.

the pin diagram of the not gate ic 7404 is depicted in the following figure.

applications of not gate

the not gate is an essential building block of various digital systems and circuits. some key applications of not gate are described below −

not gate is used in inverters to convert a high signal to a low signal and a low signal to a high signal.
not gate is used in communication systems and storage devices.
not gate is also employed as interfacing device between different logic families.
not gate is also used in various digital circuits like timers, oscillators, multivibrators, modulators, etc.

conclusion

in conclusion, the not gate is a logic gate used in digital electronics to implement inversion operation. it has only one input line and one output line.

the output of the not gate is the complement of the input signal applied to it. in this chapter, we explained the basic theory of not gate along with its working and applications.

a logic gate that can implement any kind of possible boolean function is called a universal gate. there are two universal logic gates namely, nand gate and nor gate.

these two gates are called universal gates because they can perform the function of any other logic gate like and, or, not, xor, and xnor without need of any other type of logic gate. for example, we can perform the and gate function by using only nand gates or only nor gates.

in this chapter, we will study the theory and working of the universal gates, i.e., nand gate and nor gate.

what is a nand gate?

the nand gate is a universal gate that basically a combination of two basic logic gates namely, and gate and not gate. it is designed by connecting a not gate to the output line of the and gate, as shown in the following figure.

the nand gate can have two or more input lines and one output line. the output of the nand gate is low or logic 0 only when all its inputs are high or logic 1. otherwise, the output of the nand gate is high or logic 1.

the nand gate is basically a logic gate that performs the inverse operation of an and gate.

being a universal gate, the nand gate can implement any possible boolean function or operation of any other type of logic gate.

logic symbol of nand gate

the logic symbols of a two-input and three-input nand gates are depicted in the following figure.

here, the bubble at the output side represents the inversion operation.

the variables a, b, and c designate the input lines and the variable y represents the output line of the nand gate.

truth table of nand gate

truth table is a table of inputs and outputs of a nand gate showing the relationship between them. here is the truth table of a two-input nand gate −

input		output
a	b	y
0	0	1
0	1	1
1	0	1
1	1	0

the truth table for a three-input nand gate is given below −

input			output
a	b	c	y
0	0	0	1
0	0	1	1
0	1	0	1
0	1	1	1
1	0	0	1
1	0	1	1
1	1	0	1
1	1	1	0

from these two truth tables, we can observe that the nand gate produces a low or logic 0 output only when all its inputs are high or logic 1. for any other input combinations, the output is high or logic 1.

boolean expression of nand gate

the boolean expression is a logical function that describes the logical relationship between inputs and output of a nand gate.

the boolean expression for a two-input nand gate is give below −

$$\mathrm{y \: = \: \overline{ab} \: = \: (ab)'}$$

the boolean expression for a three-input nand gate is given by,

$$\mathrm{y \: = \: \overline{abc} \: = \: (abc)'}$$

here, a, b, and c are the input variables and y is the output variable.

working of nand gate

the working of a two-input nand gate for different input combinations is described below −

if a = 0 and b = 0, the output of the nand gate is y = 1.
if a = 0 and b = 1, the output of the nand gate is y = 1.
if a = 1 and b = 0, the output of the nand gate is y = 1.
if a = 1 and b = 1, the output of the nand gate is y = 0.

similarly, the working of a three-input nand gate can be explained as below −

if a = 0, b = 0, and c = 0 the output of the nand gate is y = 1.
if a = 0, b = 0, and c = 1 the output of the nand gate is y = 1.
if a = 0, b = 1, and c = 0 the output of the nand gate is y = 1.
if a = 0, b = 1, and c = 1 the output of the nand gate is y = 1.
if a = 1, b = 0, and c = 0 the output of the nand gate is y = 1.
if a = 1, b = 0, and c = 1 the output of the nand gate is y = 1.
if a = 1, b = 1, and c = 0 the output of the nand gate is y = 1.
if a = 1, b = 1, and c = 1 the output of the nand gate is y = 0.

this is all about the operation of a nand gate for different input combinations.

it is also important to note that in this chapter, we are discussing the theory of nand gate by considering only two and three input variables. but the same logic and theory is applicable to any number of inputs.

nand gate using transistor

we can implement the nand gate logic by using bjt transistors. such a nand gate is referred to as a transistor nand gate.

the transistor circuit diagram of a two-input nand gate is shown in the following figure.

working of transistor nand gate

the working of this transistor nand gate for different input combinations is explained below −

when both inputs a and b are connected to a low signal, the transistors q₁ and q₂ act as open switches. the entire supply voltage will appear at the output line y. hence, for this input combination, the output of the circuit is high or logic 1.

when the input a is at low level and the input b is at high level, the transistor q₁ acts as an open switch and the transistor q₂ acts as a closed switch. in this case, there is not a direct connection between power supply and the ground terminal. hence, the whole supply voltage will appear at the output terminal y, making it high or logic 1.

when the input a is at high level and the input b is at low level, the transistor q₁ acts as a closed switch and the transistor q₂ acts as an open switch. again, there is a disconnection between power supply and the ground terminal. for this combination of inputs, the entire supply voltage will appear at the output line and sets the output high or logic 1.

when the both inputs are connected to a high or logic 1 signal, both transistors will turn on and connects the output line directly to the ground terminal i.e., to a low potential. this makes the output of the circuit low or logic 0.

hence, the output of this circuit is low or logic 0, only when all inputs are high or logic 1, otherwise the output is high or logic 1. thus, this circuit implements the nand gate logic.

nand gate using switches

we can also realize the nand gate using electric switches, a battery, and a lamp. the circuit diagram of a two-input nand gate using switches is shown in the following figure.

in this switching circuit, when both switches a and b are closed, there is a short-circuited path for the flow of electric current that bypasses the lamp. hence, no current will flow through the lamp and the lamp will not glow. this represents the low or logic 0 output.

for any other switching arrangement, such as a is closed and b is open, a is open and b is closed, or a and b are open. there is no short-circuited path and the entire current will flow through the lamp, making it turn on. this represents the high or logic 1 output.

thus, the output of this switching circuit is low or logic 0 only when both switches are closed, otherwise the output is high or logic 1. hence, this circuit acts as a nand gate.

we can add more switches in series with a and b to implement a higher order nand gate.

nand gate as an inverter

the nand gate can also be used as an inverter gate. for this, all its inputs are joined together and the input signal to be inverted is applied to the common terminal as shown in the following figure.

applications of nand gate

the nand gate is used in a variety of digital and automated systems. some of them are listed below −

alarm circuits
buzzer and burglar devices
automatic temperature regulation systems
security systems
automated doors and windows, etc.

this is all about the nand gate, its working and applications. let us now discuss the theory of another universal gate named, nor gate.

what is a nor gate?

the nor gate is another universal gate used in digital electronics to implement boolean functions. it is a combination of two basic logic gates namely, or gate and not gate. the nor gate is designed by connecting a not gate to the output line and the final output is taken from the output line of the not gate as shown in the following figure.

being a universal logic gate, it can be used to implement any possible boolean function or the other logic gates single-handedly.

the nor gate can have two or more input lines and one output line. the output of the nor gate is high or logic 1 only when all its inputs are low or logic 0. for all other input combinations, the output of the nor gate is low or logic 0.

logic symbol of nor gate

the logic symbols of a two-input and three-input nor gates are shown in the following figure.

here, a, b, and c are the input lines and y is the output line. the bubble at the output end represents the inversion operation.

truth table of nor gate

the truth table of the nor gate specifies the output for different input combinations. the truth table of a two-input nor gate is given below −

input		output
a	b	y
0	0	1
0	1	0
1	0	0
1	1	0

the following is the truth table of a three-input nor gate −

input			output
a	b	c	y
0	0	0	1
0	0	1	0
0	1	0	0
0	1	1	0
1	0	0	0
1	0	1	0
1	1	0	0
1	1	1	0

from these truth tables, we can observe that the output of the nor gate is high or logic 1 only when all its inputs are low or logic 0, otherwise the output is low or logic 0.

working of nor gate

the operation of a two-input nor gate for all possible input combinations is explained below −

if a = 0 and b = 0, the output of the nor gate is y = 1.
if a = 0 and b = 1, the output of the nor gate is y = 0.
if a = 1 and b = 0, the output of the nor gate is y = 0.
if a = 1 and b = 1, the output of the nor gate is y = 0.

similarly, the operation of the three-input nor gate can be described, as below −

if a = 0, b = 0, and c = 0 the output of the nor gate is y = 1.
if a = 0, b = 0, and c = 1 the output of the nor gate is y = 0.
if a = 0, b = 1, and c = 0 the output of the nor gate is y = 0.
if a = 0, b = 1, and c = 1 the output of the nor gate is y = 0.
if a = 1, b = 0, and c = 0 the output of the nor gate is y = 0.
if a = 1, b = 0, and c = 1 the output of the nor gate is y = 0.
if a = 1, b = 1, and c = 0 the output of the nor gate is y = 0.
if a = 1, b = 1, and c = 1 the output of the nor gate is y = 0.

from this discussion, we can observe that the nor gate produces a high or logic 1 output when all its inputs are low or logic 0.

nor gate using transistor

we can implement the nor gate using transistors. the circuit diagram of a two-input nor gate using transistors is shown in the following figure. this circuit is known as transistor nor gate.

working of transistor nor gate

the working of the transistor nor gate is explained below −

when both inputs a and b are low, the transistors q₁ and q₂ do not conduct and act as open switches. in this case, the output line y will directly connect to the power supply. thus, the whole supply voltage will appear at the output terminal. this makes the output of the circuit high or logic 1.

when the input a is connected to low and the input b is connected to a high signal, the transistor q₁ will act as an open switch while the transistor q₂ will act as a closed switch. in this case, the output line y will directly connect to the ground terminal through the transistor q₂. this results in a low signal at the output line.

when the input a is connected to high and the input b is connected to a low signal, the transistor q₁ will conduct and the transistor q₂ will act as an open switch. in this case, the output line is directly connected to the ground terminal. thus, the output is low or logic 0.

when both inputs a and b are connected to a high signal, both transistors q₁ and q₂ will act as closed switches and connect the output line directly to the ground terminal. in the case also, the output is low or logic 0.

from this discussion, we can observe that this transistor circuit implements the nor logic and hence called as transistor nor gate.

we can add more transistors to the circuit to obtain a higher order nor gate.

nor gate using switches

we can also realize the nor gate using electrical switches. a circuit diagram for a two-input nor gate using switches is shown in the following figure.

in this circuit, if both switches a and b are open, the entire current flows through the lamp and turn it on. this represents the high or logic 1 state of the output.

if both or any of the switches is closed, there is a short-circuited path for the flow of current that bypasses the lamp. in this case, the lamp will not glow and represent the low or logic 0 state of the output.

thus, the output of this switching circuit is high or logic 1, only when both of its inputs are low i.e., open switches, otherwise the output is low or logic 0.

therefore, this electric circuit realizes the nor gate operation and logic.

nor gate as an inverter

the nor gate also be operated as an inverter gate. to use the nor gate as an inverter, all its inputs are connected together and the input signal is applied to the common terminal as shown in the following figure.

applications of nor gate

the nor gate is used in numerous digital systems. some common applications of nor gate are listed below −

various digital systems
industrial automation and control systems
traffic control systems
alarm circuits
digital arithmetic circuits like adders and subtractors, etc.

conclusion

in conclusion, a universal logic gate is one that can implement any possible boolean functions or other logic gates without need of any other type of logic gates. in digital electronics, there are two universal logic gates namely, nand gate and nor gate.

in this chapter, we explained the theory, working, and applications of these two universal gates. here, we covered only two and three-input nand and nor gates, but the same theory and explanation is equally valid for nand and nor gates with more than three inputs.

in digital electronics, the xor gate is a derived logic gate used to determine the dissimilarity between two signals.

in chapter, we will study the theory and operation of xor gate. lets get started with the basic definition of xor gate.

what is an xor gate?

the xor gate is a type of logic gate in digital electronics which has two inputs and one output. the output of the xor gate is high or logic 1, only when both the inputs are different. for the same inputs, the output of the xor gate is low or logic 0.

xor gate is also called exclusive or gate or ex-or gate. this logic gate is widely used in digital arithmetic circuits like adders and subtractors.

since the output of the xor gate is high only when both of the inputs are dissimilar, it is also known as the inequality detector.

it is very important to note that there is no such thing like three or more input xor gate. hence, when we need xor gate for more than two input variables, we use two or more two-input xor gates.

logic symbol of xor gate

the logic symbol of an xor gate is shown in the following figure.

it has only two inputs designated as a and b and one output denoted by y.

truth table of xor gate

the truth table of xor gate is a table that represents the relationship between its inputs and output.

the truth table of an xor gate is given below −

inputs		output
a	b	y
0	0	0
0	1	1
1	0	1
1	1	0

from this truth table, we can observe that the output of the xor gate is high or logic 1 only when the both inputs are different. in the case, when both inputs are similar the output is low or logic 0.

boolean expression of xor gate

the boolean expression is a logical function that represents the relationship between inputs and output of an xor gate mathematically.

the following equation is known as the boolean expression of the xor gate.

$$\mathrm{y \: = \: a \oplus b}$$

this equation can also be expressed as below −

$$\mathrm{y \: = \: ab' \: + \: a'b \: = \: a \bar{b} \: + \: \bar{a}b}$$

here, the symbol "$\mathrm{\oplus}$" denotes the xor operation.

working of xor gate

the detailed working of xor gate for different input combinations is explained below −

if a = 0 and b = 0, the output of the xor gate is y = 0.
if a = 0 and b = 1, the output of the xor gate is y = 1.
if a = 1 and b = 0, the output of the xor gate is y = 1.
if a = 1 and b = 1, the output of the xor gate is y = 0.

from this explanation, we can see the output of xor gate is high or logic 1 only when inputs are dissimilar.

xor gate as an inverter

the xor gate can also be used as an inverter. there is a property of xor operation that is,

$$\mathrm{a \: \oplus \: 1 \: = \: \bar{a}}$$

hence, by utilizing this property, we can state that if one of the input lines of the xor gate is connected to logic 1 and the input signal is applied to another input line. then, the xor gate produces the inverted version of the applied signal as the output.

the following figure shows the operation of xor gate as an inverter.

xor gate as a buffer

a buffer gate is a logic gate that produces the same output as the input. it is used to provide some delay in the input and output.

there is a property of xor logic that is,

$$\mathrm{a \: \oplus \: 0 \: = \: a}$$

hence, if one of the two input lines of the xor gate is connected to a logic 0 and the input signal is applied to another input line. the xor gate then produces the output same as the input.

the operation of the xor gate as a buffer logic is illustrated in the following figure.

xor gate using switches

we can also implement the xor gate logic using a battery, two simple switches, and a lamp.

the following figure depicts the circuit diagram of the xor gate using switches.

in this switching circuit, if the switches a and b are on the same level (either 0 or 1), the lamp will not glow. this state represents the low or logic 0 output.

if the switches a and b are at different levels, i.e., a is at 0 and b is at 1 or a is at 1 and b is at 0. then, we can see there is a closed path for current to flow through the lamp, making the lamp turn on. this represents the high or logic 1 output.

hence, the above shown electrical circuit implements the xor logic function.

applications of xor gate

the following are some key applications of the xor gate −

xor gate is used in computational and arithmetic circuits like adders, subtractors, etc.
xor gate is used to detect errors, similarities and dissimilarities between two logic levels or signals.
xor gate is used as a controlled inverter or buffer logic.

conclusion

in conclusion, the xor gate is a two input and one output logic gate that produces a high or logic 1 output when the inputs applied to it are dissimilar.

the xor gate logic is widely used in staircase electric wiring and many other automation circuits, where a single device like lamp has to be controlled from two different locations.

an xnor gate is a type of derived logic gate which is a combination of an xor gate and a not gate. hence, it produces a "noted xor" output.

in this chapter, we will explain the basic theory of xnor logic gate, its working, circuit diagrams, and applications. so, lets start with the basic definition of xnor gate.

what is xnor gate?

the xnor gate is a logic gate that has two inputs and one output.

the output of the xnor gate is high, only when both of its inputs same, i.e., either both inputs are high or both inputs are low. if the inputs are dissimilar, i.e., one is high and the other low, the output is low or logic 0.

since the xnor gate produces a high output when both its inputs are similar, it is also known as an equality detector.

the xnor gate is also known as exclusive-nor or ex-nor gate.

actually, the xnor gate is a combination of two logic gates namely, xor gate and not gate. therefore,

xnor gate = xor gate + not gate

it is important remember that there is no such thing like an xnor gate with three or more inputs. to obtain an xnor gate with inputs more than two, we combine multiple two-input xnor gates together.

logic symbol of xnor gate

the logic symbol for a two input xnor gate is shown in the following figure.

the bubble on the right-end represents the not operation. the variables a and b represent the input lines while y represents the output line.

truth table of xnor gate

the truth table of an xnor gate provides information about the operation and relationship between inputs and output of it.

the truth table of a two-input xnor gate is given below −

input		output
a	b	y
0	0	1
0	1	0
1	0	0
1	1	1

from this truth table, it can be observed that the xnor gate produces a high or logic 1 output when both of its inputs are same i.e., 0 and 0 or 1 and 1. otherwise, it gives a low or logic 0 output.

boolean expression of xnor gate

the boolean expression is a logical function that describes the relationship between inputs and output of an xnor gate mathematically.

the boolean expression of a two-input xnor gate is given below −

$$\mathrm{y \: = \: a \: \odot \: b}$$

this can also be expressed as,

$$\mathrm{y \: = \: ab \: + \: \bar{ab}}$$

here, a and b are input variables while y is the output variable.

working of xnor gate

the operation of a two-input xnor gate for different input combinations is explained below −

if a = 0 and b = 0, the output of the xnor gate is y = 1.
if a = 0 and b = 1, the output of the xnor gate is y = 0.
if a = 1 and b = 0, the output of the xnor gate is y = 0.
if a = 1 and b = 1, the output of the xnor gate is y = 1.

hence, we can see that the output is high or logic 1 for similar inputs. it is low or logic 0 for dissimilar inputs.

xnor gate using switches

we can realize the xnor gate logic with the help of two switches, a battery, and a lamp.

here is the electrical circuit representing the xnor logic gate.

in this circuit, when both switches a and b are at same level i.e., at 0 and 0 or 1 and 1. there is a closed path for the current to flow through the lamp. this turns on the lamp and represents the high or logic 1 output.

if the switches are at different levels i.e., one is at level 0 and the other is at level 1. there is no complete path between the battery and lamp. hence, the lamp will not glow and represent the low or logic 0 output.

hence, the above shown switching circuit implements the xnor logic operation.

xnor gate as an inverter

the xnor gate can operate as an inverter. if we connect one of the input lines of the xnor gate at low or logic 0 signal and we apply the input signal to another input line. then, the output of the xnor gate will be the complement of the input applied.

the logic circuit of an xnor gate working as an inverter is depicted in the following figure.

we can also explain this operation with the help of its boolean expression as below.

$$\mathrm{y \: = \: ab \: + \: \bar{ab}}$$

if b is set at logic 0, then

$$\mathrm{y \: = \: a\cdot0 \: + \: \bar{a}\cdot1 \: = \: \bar{a}}$$

hence, if one input xnor gate is tied to logic 0, then the gate will work as an inverter.

xnor gate as a buffer

the xnor gate can also operate as a buffer. if we connect of one of the inputs of the xnor gate to logic 1 and the input signal is applied to another input line. the output of the xnor gate will be same as the input applied, i.e., the xnor gate will work as a buffer.

the xnor gate working as a buffer is shown in the following figure.

logically, we can prove this operation through its boolean expression as below.

$$\mathrm{y \: = \: ab \: + \: \bar{ab}}$$

if b is set at logic 1, then

$$\mathrm{y \: = \: a\cdot1 \: + \: \bar{a}\cdot0 \: = \: a}$$

thus, an xnor gate with one input set to logic 1 acts as a buffer.

applications of xnor gate

the xnor gate is widely used in numerous digital circuits and systems. some of the key applications of xnor gate are given below −

xnor gate is used in digital communication systems to detect errors that occurred during data transmission.
xnor gate acts as an equality detector. thus, it is also used to compare binary data or signals.
xnor gate is also used to design digital gaming systems and logic puzzles.

conclusion

in conclusion, the xnor gate or exclusive nor gate is a logic gate used in various digital electronic applications. it is a two-input logic gate.

the unique functionality of the xnor gate of equality detection is widely used in digital signal comparison and data transmission error checking.

in this chapter, we explained the basic theory and working of the xnor gate along with its key applications.

what is a logic gate?

in digital circuits, a logic gate is a fundamental element of the digital circuit or system, that performs a specific logical operation. a logic gates typically has one or more inputs and only one output. the output of the logic gate is related to the inputs based on a certain logic.

some commonly used logic gates are: and gate, or gate, not gate, nand gate, and nor gate.

what is cmos technology?

cmos, complementary metal oxide semiconductor, is a predominant technology used for manufacturing integrated circuits (ics). this technology is widely used for manufacturing a variety of digital electronic components like microprocessors, sensors, logic gates, and more.

cmos technology employs both nmos (n-channel metal oxide semiconductor) and pmos (p-channel metal oxide semiconductor) logic to implement different types of digital functions.

cmos technology is widely being used in realizing digital logic gates due to its key advantages, such as fast switching speed, low power consumption, high voltage range, high noise margins, etc.

basic cmos logic gates

let us now discuss the basic cmos logic gates in detail.

cmos or gate

the or gate is a basic logic gate in digital electronics. or gates produce a high or logic 1 output when any of its inputs is high, and it produces a low or logic 0 output when all of its inputs are low.

the truth table of a two-input or gate is given below.

input		output
a	b	y = a + b
0	0	0
0	1	1
1	0	1
1	1	1

the implementation of a two input or gate in cmos logic is shown in the following figure.

here, we have combined multiple cmos inverters together to build a cmos or gate. in the circuit diagram, the cmos or gate consists of a pmos transistor and an nmos transistor, which are joined in parallel fashion between the power supply voltage (v) and the output.

in the above circuit, when one or both inputs (a and b) are high (logic 1), the corresponding pmos and nmos transistors switch in a way that the current flows from the output to ground, causes a low voltage (logic 0) at the output terminal.

when both inputs are low (logic 0), the corresponding cmos transistors switch in a way that the output is connected to the supply voltage, causing a high voltage (logic 1) at the output terminal.

cmos and gate

the and gate is a basic logic gate used in a variety of digital logic circuits. and gate produces a high or logic 1 output only when all of its inputs are high, it produces a low or logic 0 output when any of its inputs is low.

the truth table of the two-input and gate is given below.

input		output
a	b	y = ab
0	0	0
0	1	0
1	0	0
1	1	1

the implementation of and gate using cmos technology is shown in the following figure.

here, to implement the cmos and gate, we have connected multiple cmos inverters together. in the cmos and gate circuit, pmos and nmos transistors are used to build it. these transistors are connected in series between supply voltage (v) and the output (y), and in parallel between the output and ground respectively.

in the case of cmos and gate shown in the above figure, when both inputs are high (logic 1), the cmos transistors switch in such a way that the output is connected to the power supply voltage (v), producing a high (logic 1) output.

when any of its inputs is low, the cmos transistors in the circuit switch such that the current flows from power supply to the ground, making output low (logic 0).

cmos not gate

a not gate is also a basic logic gate used in digital logic circuits. the not has a single input and a single output. the output of the not gate is high or logic 1 when its input is low or logic 0, and its output is low or logic 0 when its input is high or logic 1.

in cmos logic gates, the cmos not gate is the simplest cmos logic gate. it is also called cmos inverter gate.

the truth table of the not gate is given below.

input	output
a	y = a'
0	1
1	0

the implementation of a not gate in cmos technology is shown in the following figure.

here, the input is applied to the gate terminal of the two cmos transistor, and the output is connected to their drain terminals.

when a positive voltage pulse (logic 1) is applied to the input v_i, the cmos transistor q₁ is off and the cmos transistor q₂ is on. therefore, the output voltage will be at ground voltage, i.e. logic 0.

when the ground voltage (logic 0) is applied to the input v_i, the cmos transistor q₁ is on and the cmos transistor q₂ is off. thus, the output will be closed to +v, i.e. logic 1.

the maximum number of levels that are present between inputs and output is two in two level logic. that means, irrespective of total number of logic gates, the maximum number of logic gates that are present (cascaded) between any input and output is two in two level logic. here, the outputs of first level logic gates are connected as inputs of second level logic gate(s).

consider the four logic gates and, or, nand & nor. since, there are 4 logic gates, we will get 16 possible ways of realizing two level logic. those are and-and, and-or, andnand, and-nor, or-and, or-or, or-nand, or-nor, nand-and, nand-or, nandnand, nand-nor, nor-and, nor-or, nor-nand, nor-nor.

these two level logic realizations can be classified into the following two categories.

degenerative form
non-degenerative form

degenerative form

if the output of two level logic realization can be obtained by using single logic gate, then it is called as degenerative form. obviously, the number of inputs of single logic gate increases. due to this, the fan-in of logic gate increases. this is an advantage of degenerative form.

only 6 combinations of two level logic realizations out of 16 combinations come under degenerative form. those are and-and, and-nand, or-or, or-nor, nand-nor, nornand.

in this section, let us discuss some realizations. assume, a, b, c & d are the inputs and y is the output in each logic realization.

and-and logic

in this logic realization, and gates are present in both levels. below figure shows an example for and-and logic realization.

we will get the outputs of first level logic gates as y₁ = ab and y₂ = cd

these outputs, y₁ and y₂ are applied as inputs of and gate that is present in second level. so, the output of this and gate is

$$\mathrm{y\:=\:y_{1}y_{2}}$$

substitute y₁ and y₂ values in the above equation.

$$\mathrm{y \: = \: (ab)(cd)}$$

$$\mathrm{\rightarrow \: y \: = \: abcd}$$

therefore, the output of this and-and logic realization is abcd. this boolean function can be implemented by using a 4 input and gate. hence, it is degenerative form.

and-nand logic

in this logic realization, and gates are present in first level and nand gate(s) are present in second level. the following figure shows an example for and-nand logic realization.

previously, we got the outputs of first level logic gates as y₁ = ab and y₂ = cd

these outputs, y₁ and y₂ are applied as inputs of nand gate that is present in second level. so, the output of this nand gate is

$$\mathrm{y \: = \:(y_{1}y_{2})'}$$

substitute y₁ and y₂ values in the above equation.

$$\mathrm{y \: = \: ((ab)(cd))'}$$

$$\mathrm{\rightarrow \: y \: = \: (abcd)'}$$

therefore, the output of this and-nand logic realization is (abcd)'. this boolean function can be implemented by using a 4 input nand gate. hence, it is degenerative form.

or-or logic

in this logic realization, or gates are present in both levels. the following figure shows an example for or-or logic realization.

we will get the outputs of first level logic gates as y₁ = a + b and y₂ = c + d.

these outputs, y₁ and y₂ are applied as inputs of or gate that is present in second level. so, the output of this or gate is

$$\mathrm{y \:= \: y_{1}\:+\:y_{2}}$$

substitute y₁ and y₂ values in the above equation.

$$\mathrm{y \: = \: (a\:+\:b) \: + \: (c\:+\:d)}$$

$$\mathrm{\rightarrow \: y \:=\:a\:+\:b\:+\:c\:+\:d}$$

therefore, the output of this or-or logic realization is a + b + c + d. this boolean function can be implemented by using a 4 input or gate. hence, it is degenerative form.

similarly, you can verify whether the remaining realizations belong to this category or not.

non-degenerative form

if the output of two level logic realization can't be obtained by using single logic gate, then it is called as non-degenerative form.

the remaining 10 combinations of two level logic realizations come under nondegenerative form. those are and-or, and-nor, or-and, or-nand, nand-and, nandor, nand-nand, nor-and, nor-or, nor-nor.

now, let us discuss some realizations. assume, a, b, c & d are the inputs and y is the output in each logic realization.

and-or logic

in this logic realization, and gates are present in first level and or gate(s) are present in second level. below figure shows an example for and-or logic realization.

previously, we got the outputs of first level logic gates as y₁ = ab and y₂ = cd.

these outputs, y₁ and y₂ are applied as inputs of or gate that is present in second level. so, the output of this or gate is

$$\mathrm{y\:=\:y_{1}\:+\:y_{2}}$$

substitute y₁ and y₂ values in the above equation

$$\mathrm{y\:=\:ab\:+\:cd}$$

therefore, the output of this and-or logic realization is ab + cd. this boolean function is in sum of products form. since, we cant implement it by using single logic gate, this and-or logic realization is a non-degenerative form.

and-nor logic

in this logic realization, and gates are present in first level and nor gate(s) are present in second level. the following figure shows an example for and-nor logic realization.

we know the outputs of first level logic gates as y₁ = ab and y₂ = cd

these outputs, y₁ and y₂ are applied as inputs of nor gate that is present in second level. so, the output of this nor gate is

$$\mathrm{y \:=\:(y_{1}\:+\:y_{2})'}$$

substitute y₁ and y₂ values in the above equation.

$$\mathrm{y\:=\:(ab\:+\:cd)'}$$

therefore, the output of this and-nor logic realization is (ab + cd)'. this boolean function is in and-or-invert form. since, we cant implement it by using single logic gate, this and-nor logic realization is a non-degenerative form

or-and logic

in this logic realization, or gates are present in first level & and gate(s) are present in second level. the following figure shows an example for or-and logic realization.

previously, we got the outputs of first level logic gates as y₁ = a + b and y₂ = c + d.

these outputs, y₁ and y₂ are applied as inputs of and gate that is present in second level. so, the output of this and gate is

$$\mathrm{y\:=\:y_{1}y_{2}}$$

substitute y₁ and y₂ values in the above equation.

$$\mathrm{y \: = \: (a\:+\:b)(c\:+\:d)}$$

therefore, the output of this or-and logic realization is (a + b) (c + d). this boolean function is in product of sums form. since, we cant implement it by using single logic gate, this or-and logic realization is a non-degenerative form.

similarly, you can verify whether the remaining realizations belong to this category or not.

in previous chapters, we have implemented various combinational circuits using logic gates. except not gate, the remaining all logic gates have at least two inputs and single output. similarly, the threshold gate also contains at least one input and only one output.

additionally, it contains the respective weights to each input and a threshold value. the values of these weights and threshold could be of any finite real number.

basics of threshold gate

let the inputs of threshold gate are x₁, x₂,x₃,, x_n. the corresponding weights of these inputs are w₁, w₂,w₃, , w_n. the symbol of threshold gate is shown in the following figure.

threshold gate is represented with a circle and it is having 'n' inputs, x₁ to x_n and single output, y. this circle is made into two parts. one part represents the weights corresponding to the inputs and other part represents threshold value, t.

the sum of products of inputs with corresponding weights is known as weighted sum. if this weighted sum is greater than or equal to threshold value, t then only the output, y will be equal to one. otherwise, the output, y will be equal to zero.

mathematically, we can write this relationship between inputs and output of threshold gate as below.

$$\mathrm{y \: = \: 1 \:\: if \: \: w_{1}x_{1} \: + \: w_{2}x_{2} \: + \: w_{3}x_{3} \: + \: \dotso \: + \: w_{n}x_{n} \: \geq \: t}$$

= 0, otherwise.

therefore, we can implement various logic gates and boolean functions just by changing the values of weights and / or threshold value, t.

example

let us find the simplified boolean function for the following threshold gate.

this threshold gate is having three inputs x₁, x₂, x₃ and one output y.

the weights corresponding to the inputs x₁, x₂ & x₃ are w₁ = 2, w₂ = 1 & w₃ = -4 respectively.

the value of threshold gate is t = -1.

the weighted sum of threshold gate is

$$\mathrm{w \: = \: w_{1}x_{1} \: + \: w_{2}x_{2} \: + \: w_{3}x_{3}}$$

substitute the given weights in the above equation.

$$\mathrm{\rightarrow \: w \: = \: 2x_{1} \: + \: x_{2} \: − \: 4x_{3}}$$

output of threshold gate, y will be '1' if w &geq; 1, otherwise it will be '0'.

the following table shows the relationship between the input and output for all possible combination of inputs.

input			weighted sum	output
x₁	x₂	x₃	w = 2x₁ + x₂ - 4x₃	y
0	0	0	0	1
0	0	1	-4	0
0	1	0	1	1
0	1	1	-3	0
1	0	0	2	1
1	0	1	-2	0
1	1	0	3	1
1	1	1	-1	1

from the above table, we can write the boolean function for output, y as

$$\mathrm{y \: = \: \sum m( 0,2,4,6,7)}$$

the simplification of this boolean function using 3 variable k-map is shown in the following figure.

therefore, the simplified boolean function for given threshold gate is y = x₃' + x₁ x₂.

synthesis of threshold functions

threshold gate is also called as universal gate because we can implement any boolean function using threshold gate(s). some-times, it may not possible to implement few logic gates and boolean functions by using single threshold gate. in that case, we may require multiple threshold gates.

follow these steps for implementing a boolean function using single threshold gate.

step 1 − formulate a truth table for given boolean function.

step 2 − in the above truth table, add (include) one more column, which gives the relation between weighted sums and threshold value.

step 3 − write the relation between weighted sums and threshold for each combination of inputs as mentioned below.

if the output of boolean function is 1, then the weighted sum will be greater than or equal to threshold value for those combination of inputs.
if the output of boolean function is 0, then the weighted sum will be less than threshold value for those combination of inputs.

step 4 − choose the values of weights & threshold in such a way that they should satisfy all the relations present in last column of the above table.

step 5 − draw the symbol of threshold gate with those weights and threshold value.

example

let us implement the following boolean function using single threshold gate.

$$\mathrm{y( x_{1},x_{2},x_{3})\:=\: \sum m ( 0,2,4,6,7)}$$

the given boolean function is a three variable function, which is represented in sum of min terms form. the truth table of this function is shown below.

input			output
x₁	x₂	x₃	y
0	0	0	1
0	0	1	0
0	1	0	1
0	1	1	0
1	0	0	1
1	0	1	0
1	1	0	1
1	1	1	1

now, let us add (include) one more column to the above truth table. this last column contains the relations between weighted sums (w) and threshold value (t) for each combination of inputs.

input			output	relations between w & t
x₁	x₂	x₃	y	relations between w & t
0	0	0	1	$\mathrm{0 \: \geq \: t}$
0	0	1	0	$\mathrm{w_{3} \: \lt \: t}$
0	1	0	1	$\mathrm{w_{2} \: \geq \: t}$
0	1	1	0	$\mathrm{w_{2}+w_{3} \: \lt \: t}$
1	0	0	1	$\mathrm{w_{1} \: \geq \: t}$
1	0	1	0	$\mathrm{w_{1}+w_{3} \: \lt \: t}$
1	1	0	1	$\mathrm{w_{1}+w_{2} \: \geq \: t}$
1	1	1	1	$\mathrm{w_{1}+w_{2}+w_{3} \: \geq \: t}$

following are the conclusions from the above table.

the value of threshold should be either zero or negative based on first relation.
the value of w₃ should be negative based on first and second relations.
the values of w₁ and w₂ should be greater than or equal threshold value based on fifth and third relations.
w₂ should be greater than w₃ based on fourth relation.

we can choose the following values for weights and threshold based on the above conclusions.

w₁ = 2, w₂ = 1, w₃ = -4 & t = -1

the symbol of threshold gate with the above values is shown below.

therefore, this threshold gate implements the given boolean function, $\mathrm{y( x_{1}, x_{2},x_{3}) \:=\: \sum m (0,2,4,6,7)}$.

boolean algebra is a branch of mathematics that provides a set of operations and rules to manipulate and process binary variables. it is considered the foundation of digital electronics and computer science.

boolean algebra is based on the binary number system. in this chapter, we will cover the basic theory of boolean algebra, its significance, advantages, limitations, and applications.

what is boolean algebra?

boolean algebra is a mathematics that provides various operators and rules to perform arithmetic and algebraic operations on binary variables and numbers. the boolean algebra is based on the binary number system and logical arithmetic. thus, it is also referred to as logical algebra.

boolean algebra was developed by a mathematician and logician george boole in the year of 1847.

today, boolean algebra is being used as the fundamental of digital electronics, computer systems, and information technology.

since, boolean algebra is based on the binary number system. hence, the boolean variables can take only two possible values i.e., 0 and 1. here, the value 0 represents the false state, while the value 1 represents the true state.

the operations in boolean algebra are based on the three fundamental logical operations namely, and, or, and not.

let us discuss about each of these three logical operations in detail.

logical operations in boolean algebra

the following are the fundamental logical operations that form the basis of boolean algebra −

and operation

in boolean algebra, a logical operation in which the outcome is true (1) only when all the input values are true (1), otherwise, the output is false (0) is termed as and operation. the and operation is represented by a dot (.). for example, a and b can be represented as a.b in symbolic form.

or operation

in boolean algebra, the or operation is another logical operation in which the output is false (0) only when all input values are false (0), otherwise the output is true (1). the or operations is denoted by a plus (+). for example, a or b can be represented as a + b.

not operation

in boolean algebra, the not operation is performed to obtain the inverted version of the input value. thus, the result of the not operation is false (0), if the input is true (1) and vice-versa. the not operation is represented by the symbol "~". for example, not a is represented as ~a.

these are the basic operations used in the boolean algebra. however, there are many more logical operations and rules that used in the boolean algebra to perform complex tasks.

terminology of boolean algebra

the following are some important terms commonly used in boolean algebra −

boolean variable

a boolean variable is a symbol that can take one of the two possible binary values i.e., 0 and 1.

boolean value

it is nothing but a value representing the state of a variable. it can be either true (1) or false (0).

boolean function or expression

it is a logical expression that consists of boolean variables and values, and logical operators like and, or, or not. it represents a logical relationship between all the elements.

logic gate

a logic gate is a digital circuit that can perform a specific logical operation. there are 7 main logic gates used in digital electronics, they are and gate, or gate, not gate, nor gate, nand gate, xor gate, and xnor gate.

these are the basic terms used in boolean algebra and provides a foundation for its understanding and working.

significance of boolean algebra in digital electronics

boolean algebra plays a crucial role in building the foundation of the digital electronics and computer science.

here is a list of some of key factors that make boolean algebra an important concept in the field of digital electronics −

boolean algebra utilizes binary number system that provides a simplified way of representing on and off states of a digital system. where, 0 is used to denote the off state, while 1 is used to represent the on state of the system.
boolean algebra provides various efficient methods like k-map, qc method, etc. to simplify complex logical operations.
boolean algebra allows to implement various arithmetic and logical operations using simple logic gates.
boolean algebra enables us to develop switching algorithms that are essential components in various computer networks and communication systems.
boolean algebra provides various rules and sets of operations used in computer programming to perform logical and decision-making operations.
boolean algebra simplifies the data storage and transmission processes.
boolean algebra provides a foundation for developing artificial intelligence and machine learning technologies.

overall, the boolean algebra creates a fundamental structure and framework to develop and implement various digital electronic systems and information-based technologies. hence, it is an important concept in the field of digital electronics.

advantages of boolean algebra

boolean algebra has numerous advantages in the field of digital electronics. some key benefits of boolean algebra are listed below −

boolean algebra provides a rich set of laws and theorems to simplify complex logical functions so that they can implemented using a smaller number of digital components. this simplification makes the digital circuits significantly cost-effective, simpler to design and implement, and low power consuming.
boolean algebra provides various tools to analyze and verify the functionality of digital systems to meet the desired requirements.
the operations based on boolean algebra can be analyzed and simulated using digital tools and software.
boolean algebra provides the logical foundation for programming and software development.
boolean algebra enables us to create, analyze, and simulate the real-world systems.
boolean algebra helps understand the working and logical implementation of digital circuits, systems, and software.

hence, all these advantages of boolean algebra make it a perfect foundation for understanding, analyzing, and designing the digital systems.

disadvantages of boolean algebra

boolean algebra is a powerful tool in terms of design and analysis of digital systems. but it also has some disadvantages.

here is a list of some of the major disadvantages of boolean algebra −

boolean algebra is based on the binary number system and is best suited for digital systems. it cannot be used in the applications where continuous representation of information is desired.
boolean algebra is based on the true or false statements. hence, it is not suitable for quantitative representation of information.
boolean algebra has a limited set of logical operations like and, or, and not.
boolean algebra becomes complex to manage in the case of large digital systems due to a greater number of variables.
boolean algebra does not provide any mean to directly represent the arithmetic operations such as addition, subtraction, multiplication, and division.
boolean algebra cannot represent the analog signals or continuous functions.
boolean algebra does not support various advanced mathematical concepts which are required in numerous engineering and scientific applications.

although it has some disadvantages, boolean algebra still forms the foundation of digital electronics and computer science.

applications of boolean algebra

boolean algebra is a fundamental tool used in a wide range of applications in the field of digital electronics. some of the key applications of boolean algebra are listed below −

boolean algebra is used to design digital circuits and systems.
boolean algebra is used to simplify and optimize the implementation and operation of digital circuits.
boolean algebra is used to develop logical concepts and control structures in computer programming and software development environment.
boolean algebra plays a vital role in the design and operation of central processing unit or cpu of a computing system.
boolean algebra also important in the field of internet and operations of search engines. it helps filtering the search queries to provide accurate results.
telecommunication systems also utilize the boolean algebra for data routing, data communication, error detection and correction purposes.
boolean algebra plays a crucial role in optimization of computer networks and their operation.
boolean algebra is also used to design control systems for automate the processes in the field of robotics and industrial automation.

these are some common examples of applications of boolean algebra. although, this list can extend to any number because boolean algebra is the foundation of digital systems and computer science.

conclusion

in conclusion, boolean algebra is a mathematics of logic that provides a set of rules and a framework to design and develop digital and logical systems.

boolean algebra is basically a tool developed to design, analyze, and optimize the digital circuits and systems. it helps simplify the design and implementation of digital circuits.

boolean algebra is an important concept in the field of digital electronics, computer programming, internet, databases, digital communication, artificial intelligence, etc.

the key feature of boolean algebra is that it can represent information in the binary form that can be processed using digital systems and computers.

in this chapter, we explained the basics of boolean algebra. in the next chapter, we will learn the laws and rules of boolean algebra.

boolean algebra is a mathematical tool that deals with logical operations and binary number system. it builds the foundation of digital electronics and computer science.

the laws and rules in boolean algebra are the sets of logical statements or expressions upon which all the logical expressions are built. each law of the boolean algebra can be interpreted as an operation performed by a logic circuit like a logic gate.

in this chapter, we will learn about laws and rules of boolean algebra that are used to simplify the logical functions and boolean expressions. these laws and rules are essential tools in boolean algebra that help to reduce the complexity and optimize the digital circuits and systems.

let us learn the primary laws and rules of boolean algebra in detail that are used to perform logical operations.

laws of boolean algebra

all the important laws and rules of boolean algebra are explained below −

rules of logical operations

there are three basic logical operations namely, and, or, and not. the following table highlights the rules associated with these three logical operations −

and operation	or operation	not operation
0 and 0 = 0	0 or 0 = 0	not of 0 = 1
0 and 1 = 0	0 or 1 = 1	not of 1 = 0
1 and 0 = 0	1 or 0 = 1
1 and 1 = 1	1 or 1 = 1

these rules of boolean algebra can be implemented using logic gates.

and laws

in boolean algebra, there are four and laws given below −

law 1 − a · 0 = 0 (this law is called null law).
law 2 − a · 1 = a (this law is called identity law).
law 3 − a · a = a
law 4 − a · a' = 0

or laws

there are four or laws described below −

law 1 − a + 0 = a (this law is called null law).
law 2 − a + 1 = 1 (this law is called identity law).
law 3 − a + a = a
law 4 − a + a' = 1

complementation laws

there are following five complementation laws in boolean algebra −

law 1 − 0' = 1
law 2 − 1' = 0
law 3 − if a = 0, then a' = 1
law 4 − if a = 1, then a' = 0
law 5 − (a')' = a (this is called double complementation law)

commutative laws

there are following two commutative laws in boolean algebra −

law 1 − according to this law, the operation a or b produces the same output as the operation b or a, i.e.,

a + b = b + a

hence, the order of the variables does not affect the or operation.

this law can be extended to any number of variables. for example, for three variables, it will be,

a + b + c = c + b + a = b + c + a = c + a + b

law 2 − according to this law, the output of the a and b operation is same as that of the b and a operation, i.e.,

a · b = b · a

this law states that the order in which the variables are anded does not affect the result.

we can extend this law to any number of variables. for example, for three variables, we get,

a · b · c = a · c · b = c · b · a = c · a · b

associative laws

associative laws define the ways of grouping the variables. there are two associative laws as described below.

law 1 − the expression a or b ored with c results the same as the a ored with b or c, i.e.,

(a + b) + c = a + (b + c)

this law can be extended to any number of variables. for example, for 4 variables, we get,

(a + b + c) + d = a + (b + c + d) = (a + b) + (c + d)

law 2 − the expression a and b anded with c results the same as the expression a anded with b and c, i.e.,

(a · b) · c = a · (b · c)

we can extend this law to any number of variables. for example, if we have 4 variables, then

(abc)d = a(bcd) = (ab)·(cd)

distributive laws

in boolean algebra, there are the following two distributive laws that allow for multiplying or factoring out of expressions.

law 1 − according to this law, we or several variables and then and the result with a single variable.

it gives the same result as the expression in which the single variable is anded with each of the several variables and then ored the product terms, i.e.,

a · (b + c) = ab + ac

we can extend this law to any number of variables. for example,

a(bc + de) = abc + ade

ab(cd + ef) = abcd + abef

law 2 − according to this law, if we and several variables and then the result is ored with a single variable.

it gives the same result as we or the single variable with each of the several variables and then the sum terms are anded together, i.e.,

a + bc = (a + b)(a + c)

proof − the proof of this law is explained here,

rhs = (a + b)(a + c)

= aa + ab + ac + bc

= a + ab + ac + bc

= a (1 + b + c) + bc

since,

1 + b + c = 1 + c = 1

therefore,

a · 1 + bc = a + bc = lhs

redundant literal rule (rlr)

under this rule, there are two laws in boolean algebra, which are explained here.

law 1 − according to this law, if we or a variable with the and of the complement of the variable and another variable. then, it is same as the or of the two variables, i.e.,

a + ab = a + b

proof − the proof of this law is explained here,

lhs = a + ab = (a + a)(a + b)

= 1 · (a + b) = a + b = rhs

law 2 − according to this law, if we and a variable with the or of the complement of the variable and another variable, it is equivalent to when we and the two variables, i.e.,

a(a + b) = ab

proof − this law can be proved as follows,

lhs = a(a + b) = aa + ab

= 0 + ab = ab = rhs

both these laws show that the complement of a term appearing in another term is redundant. hence, the rule is named as redundant literal rule.

idempotence laws

the term "idempotence" is a synonym for "same value". there are two idempotence laws in boolean algebra. they are,

law 1 − according to this law, anding a variable with itself is equal to the variable, i.e.,

a · a = a

law 2 − according to this law, oring a variable with itself is equal to the variable, i.e.,

a + a = a

absorption laws

there are two absorption laws in boolean algebra and they are explained below.

law 1 − according to this law, if we or a variable with the and of the that variable and another variable, then it is equal to the variable itself, i.e.,

a + a · b = a

this can be proved as follows,

lhs = a + a · b = a · (1 + b)

= a · 1 = a = rhs

law 2 − according to this law, the and of a variable with the or of that variable and another variable is equivalent to the variable itself i.e.,

a(a + b) = a

this can also be proved as follows,

lhs = a(a + b) = aa + ab

= a + ab = a(1 + b) = a · 1 = a = rhs

hence, this law proves that if a term appears in another term, then the latter term will become redundant and can be removed from the expression.

demorgan's theorem

in boolean algebra, demorgans theorem defines two laws which are explained below.

law 1 − according to this law, the complement of a sum of variables is equivalent to the product of complement of each of the variables, i.e.,

$$\mathrm{\overline{a+b} \: = \: \bar{a}\cdot\bar{b}}$$

this law can be extended to any number of variables.

law 2 − the second law of demorgans theorem states that the complement of a product of variables is equivalent to the sum of complement of each of the variables, i.e.,

$$\mathrm{\overline{ab} \: = \: \bar{a}\: + \:\bar{b}}$$

this law can also be extended to any number of variables.

conclusion

in this chapter, we explained all the important laws, rules, and theorems used in boolean algebra. these rules and laws are extensively used to simplify the logical expressions in digital electronics.

basically, all these rules provide a set of tools for simplification of complex boolean functions and make the digital circuits simpler.

in digital electronics, boolean function is a fundamental concept that defines the logical and mathematical relationship between input binary variables and binary result. these functions are defined as per the rules of boolean algebra and binary number system.

in this chapter, we will explain the fundamentals of boolean functions, their properties, advantages, applications. so, lets get started with a basic introduction to boolean function.

what is a boolean function?

a boolean function is a mathematical expression consists of binary variables and logical operators. it defines a logical relationship between the binary variables and binary output.

the boolean functions are defined using the rules of boolean algebra and binary number system. these functions build the foundation of design and development of digital circuits and systems.

components of a boolean function

a boolean function consists of the following two major components −

binary variables
logical operators

binary variables

a binary variable is a symbol that can take one of the two possible values i.e., 0 and 1. if a binary variable has a value 0 associated to it. then, it represents a low or false state. while if the value of the binary variable is 1, then it represents the high or true state.

logical operators

a logical operator is a symbol that represents a logical operation or process. in boolean algebra, there are three basic logical operators −

and operator

it is denoted by a dot (.). the output of the and operation is true or high or logic 1, if and only if all its input variables have a value true or high or logic 1. it is a binary operator, as it requires minimum two input variables.

or operator

it is denoted by a plus sign (+). it is also a binary operator, as minimum two input variables are required. the output of the or operation is true or high or logic 1, if any of its inputs is true or high or logic 1.

not operator

the not operator is represented by the symbol tilde (~). it is a unary operator requires only one input variable. the not operator inverts or complements the value of the input variable. thus, if the value of the input variable is 1, it gives 0 as output and vice versa.

representations of boolean functions

a boolean function can be represented in several different forms. the following are some commonly used representations of boolean functions −

mathematical form

in this form, the boolean expression is represented as a mathematical expression consisting of binary variables and logical operators in their symbol form. for example,

y(a,b,c) = ab + abc + bc

this form is also known as algebraic form.

truth table

in this form, a boolean function is represented in a tabular format. the table represents all the possible combinations of binary variables and their corresponding binary outputs of the boolean function.

for example, y = a + b is a boolean function and its truth table representation is shown below.

a	b	y
0	0	0
0	1	1
1	0	1
1	1	1

logic circuit diagram

it is the graphical representation of a boolean function. the logic circuit diagram represents a boolean function through an interconnection of logic gates. where, each logic gate is represented by using its symbol.

the logic circuit diagram of a boolean function y = ab + ac is shown in the following figure.

importance of boolean function in digital electronics

in digital electronics, boolean function is the key concept used to express a logical relation between different variables and output values. as we know, digital systems work with binary information, where the binary information is expressed using binary variables.

boolean functions provide an efficient and logical way of expressing the relationship between these binary variables, so that the system can understand and manipulate the binary information.

boolean functions also provide a basis for designing of logic gates and other digital circuits. basically, they provide a systematic and mathematical approach to design and analyze digital systems.

we can also use boolean functions to understand and verify the behavior of the digital circuits for different possible inputs. therefore, boolean functions are also utilized as the debugging and optimization tools for digital systems.

overall, boolean function is a standardized tool used in the field of digital electronics to perform various tasks, such as implementation, analysis, optimization, and verification of operation of digital circuits and systems.

characteristics of boolean functions

a boolean function has several important characteristics that makes it a crucial tool for designing, implementing, and analyzing digital circuits. some of the key characteristics of boolean functions are listed below −

boolean functions provide a simple and clear method to express a logical relationship between input variables and output of a digital system.
a boolean function can be used as an instrument to understand the behavior of a digital circuit for different input combinations.
boolean functions are composed of binary variables. hence, they can be directly realized using logic gates.
boolean functions also help determining the output of digital systems without their actual implementation.
boolean functions also play a crucial role in reducing system complexity and cost minimization.
boolean functions allow to detect and correct the errors in digital system design to improve the accuracy and reliability.

all these are the important characteristics of boolean function. apart from these advantages, boolean functions also have several limitations, which are listed in the next section.

limitations of boolean functions

here is a list of some of key limitations of boolean functions −

boolean functions are dependent on binary number system. hence, they are not suitable to represent many problems outside the field of digital electronics.
boolean functions are very sensitive to small variations in the input values. this high sensitivity can sometimes produce unpredictable results.
boolean functions cannot express the natural arithmetic operations directly.
boolean functions are not convenient for some applications like statistical modeling.

applications of boolean functions

boolean functions have a wide range of applications in the field of digital electronics and computer science.

some of key applications of boolean functions are described below −

boolean functions are used to design, analyze, and implement the digital circuits.
the design and operation of computer systems and microprocessors is defined through the boolean functions.
boolean functions are also used to express the outputs of the logic gates, flip-flops, counters, decoders, and all the other digital systems.
boolean functions are also used to design the circuits employed for digital signal processing.
boolean functions are used in electrical and electronics engineering to design, implement, and analyse the control systems, automation systems, etc.

conclusion

in conclusion, a boolean function is an elementary tool used to specify a systematic, mathematical, and logical relationship between binary variables and the output of a digital system.

boolean functions are so versatile that they can be used for various purposes such as designing, analysis, implementation, optimization, etc. of the digital systems.

in boolean algebra, several rules are defined to perform operations in digital logic circuits. boolean algebra is a tool to perform operation on binary digits, i.e. 0 and 1. these two binary digits 0 and 1 are used to denote false and true states of a digital circuit at input and output ends. boolean algebra, developed by george boole, uses 0s and 1s to create truth tables and logic expressions of digital circuits like and, or, not, etc. which are used to analyze and simplify the complex circuits.

there were another english mathematician augustus demorgan who explained the nand and nor operations as not and and not or operations respectively. this explanation was named de morgan's theorem. in this tutorial, we will discuss the demorgan's theorem in detail.

what is demorgan's theorem?

demorgan's theorem is a powerful theorem in boolean algebra which has a set of two rules or laws. these two laws were developed to show the relationship between two variable and, or, and not operations. these two rules enable the variables to be negated, i.e. opposite of their original form. therefore, demorgan's theorem gives the dual of a logic function.

now, let us discuss the two laws of demorgan's theorem.

demorgan's first theorem (law 1)

demorgan's first law states that the complement of a sum (oring) of variables is equal to the product (anding) of their individual complements. in other words, the complement of two or more ored variables is equivalent to the and of the complements of each of the individual variables, i.e.

$$\mathrm{\overline{a+b} \: = \: \bar{a} \cdot \bar{b}}$$

or, it may also be represented as,

$$\mathrm{\lgroup a \: + \: b \rgroup' \: = \: a'\cdot b'}$$

the logic implementation of left side and right side of this law is shown in figure 1.

thus, demorgan's first law proves that the nor gate is equivalent to a bubbled and gate. the following truth table shows the proof of this law.

left side			right side
input		output	input		output
a	b	(a + b)'	a'	b'	a'· b'
0	0	1	1	1	1
0	1	0	1	0	0
1	0	0	0	1	0
1	1	0	0	0	0

this truth table proves that the boolean expression on the left is equivalent to that on the right side of the expression of demorgan's first law.

also, the first law of demorgan's theorem can be extended to any number of variables, or a combination of variables.

for example,

$$\mathrm{\overline{a \: + \: b \: + \: c \: + \: d \: + \: e \: + \: \dotso} \: = \: \bar{a} \: \bar{b} \: \bar{c} \: \bar{d} \: \bar{e} \: \dotso}$$

also,

$$\mathrm{\overline{abc \: + \: de \: + \: fgh \: + \: \dotso}\: = \: \overline{\lgroup abc \rgroup}.\overline{\lgroup de \rgroup}.\overline{\lgroup fgh\rgroup}.\dotso}$$

from the above discussion, we may conclude that the demorgan's first law converts an expression from a sum form under a not sign to a product form.

demorgan's second theorem (law 2)

demorgan's second law states that the complement of the product (anding) of variables is equivalent to the sum (oring) of their individual complements.

in other words, the complement of two or more anded variables is equal to the sum of the complement of each of the individual variables, i.e.,

$$\mathrm{\overline{ab} \: = \: \overline{a} \: + \: \overline{b}}$$

it may also be represented as,

$$\mathrm{\lgroup ab \rgroup' \: = \: a' \: + \: b'}$$

the logic implementation of left and right sides of this expression is shown in figure 2.

hence, demorgan's second law proves that the nand gate is equivalent to a bubbled or gate. the following truth table shows the proof of this law.

left side			right side
input		output	input		output
a	b	ab	a'	b'	a' + b'
0	0	0	1	1	1
0	1	1	1	0	1
1	0	1	0	1	1
1	1	1	0	0	0

this truth table proves that the boolean expression on the left side is equivalent to that on the right side of the expression of demorgan's second law.

similar to the first law, we may extend the demorgan's second law for any number of variables or combination of variables.

for example,

$$\mathrm{\overline{abcde \dotso} \: = \: \overline{a} \: + \: \overline{b} \: + \: \overline{c} \: + \: \overline{d} \: + \: \overline{e} \: + \: \dotso}$$

and, for a combination of variables,

$$\mathrm{\overline{\lgroup abc \rgroup} \overline{\lgroup de \rgroup} \overline{\lgroup fg \rgroup \dotso} \: = \: \overline{abc} \: + \: \overline{de} \: + \: \overline{fg}}$$

hence, from the above discussion, we can conclude that demorgan's second law transforms a product form of variables or combination of variables under a not sign into a sum form.

therefore, demorgan's laws transforms an and operation into an or operation, and an or operation into an and operation. this principle is called duality.

example 1

apply demorgan's theorem to the following boolean expression,

$$\mathrm{f \: = \: \overline{ab \overline{ \lgroup c \: + \: d \rgroup}ef}}$$

solution

given expression is,

$$\mathrm{f \: = \: \overline{ab \overline{ \lgroup c \: + \: d \rgroup}ef}}$$

as the given expression has and operation under a not sign, thus on applying demorgan's second law, we get,

$$\mathrm{f \: = \: \overline{ab} \: + \: \lgroup c \: + \: d \rgroup \: + \: \overline{ef}}$$

this is the equivalent or the dual of the given expression.

example 2

apply demorgan's theorem to the following boolean expression,

$$\mathrm{f \: = \: \overline{ab \: + \: \overline{cd}}}$$

solution

given expression is,

$$\mathrm{f \: = \: \overline{ab \: + \: \overline{cd}}}$$

the given expression is in the form of a sum of variables under a not sign, thus on applying demorgan's first law, we get the dual of this expression.

$$\mathrm{f \: = \: \overline{ab} \cdot \overline{\overline{cd}} \: = \: \overline{ab} \cdot cd}$$

in this chapter, we explained the two laws of demorgan's theorem and showed how they are helpful in performing different operations in digital logic circuits.

before focusing on logical expression in ssop (standard sum of products) form and spos (standard product of sum) form, let us have a brief introduction the "sum of products" and "product of sum" forms.

sop (sum of products) form

the sop or sum of products form is a form of expressing a logical or boolean expression. in sop, different product terms of input variables are logically ored together. therefore, in the case of sop form, we first logically and the input variables, and then all these product terms are summed together with the help of logical or operation.

for example −

$$\mathrm{\mathit{f} \lgroup a,b,c \rgroup \: = \: abc \: + \: \bar{a}bc \: + \: ab \bar{c}}$$

this is a logical expression in three variables. here, abc, a'bc, and abc' are the three product terms which are summed together to get the expression in sop form.

pos (product of sum) form

the pos or product of sum form is another form used to represent a logical expression. in pos form, different sum terms of input variables are logically anded together. hence, if we want to express a logical expression in pos form, for that we first logically or all the input variables and then these sum terms are anded using and operation.

for example −

$$\mathrm{\mathit{f} \lgroup a,b,c \rgroup \: = \: \lgroup a \: + \: b \: + \: c \rgroup \lgroup \bar{a} \: + \: b \: + \: c \rgroup \lgroup a \: + \: b \: + \: \bar{c} \rgroup}$$

here, f is a logical expression in three variables. from this example, it can be seen that there are three sum terms which are anded together to obtain the pos form of the given expression.

now, let us discuss the standard sum of products (ssop) form and standard product of sum (spos) form in detail.

a boolean or logical expression can be represented into two standard forms namely,

ssop form
spos form

standard sum of products (ssop) form

the standard sum of products (ssop) form is a form of expressing a logical expression in which the logical expression is represented as the sum of a number of product terms where each product term will contain all the variables of the logical expression either in complemented or un-complemented form.

since, each product term of the ssop form contains all the variables, hence it is also known as expanded sum of products form. the ssop form is also known disjunctive canonical form (dcf) or canonical sum of products form or normal sum of products form.

we can simply obtain the standard sum of products form of a logical expression from the truth table by determining the sum of all the terms that correspond to those combinations for which the given logical expression (say f) has the value 1.

we can also obtain the standard sum of products (ssop) form of an expression from the sum of products (sop) form by using boolean algebra.

for example,

$$\mathrm{\mathit{f} \lgroup a,b,c \rgroup \: = \: a \bar{b} \: + \: b \bar{c}}$$

this is a logical expression in three variables, but it is expressed in sop form. we can convert this expression into ssop form using boolean algebra as follows.

$$\mathrm{\mathit{f}\lgroup a,b,c \rgroup \: = \: a \bar{b} \lgroup c \: + \: \bar{c} \rgroup \: + \: b \bar{c} \lgroup a \: + \: \bar{a} \rgroup}$$

$$\mathrm{\mathit{f}\lgroup a,b,c \rgroup \: = \: a \bar{b}c \: + \: a \bar{b} \: \bar{c} \: + \: ab \bar{c} \: + \: \bar{a}bc}$$

this is the standard sum of products form of the given logical expression. we can notice that in the ssop form, each product term contains all the variables of the logic function either in complemented or un-complemented form. each of these product terms is called a minterm. a logical function or expression in n' variables can have maximum 2ⁿ minterms. the sum of minterms of a logical expression whose value is 1 is called the standard sum of products form of the expression.

standard product of sum (spos) form

the standard product of sums (spos) form is a form of expressing a logical function in which the logical expression is represented as the product of a number of sum terms where each sum term will contain all the variables of the logical expression either in complemented or un-complemented form.

spos form is also known as conjunctive canonical form (ccf) or expanded product of sums form or normal product of sums form or canonical product of sums form.

the spos form of each term is derived by considering the combinations of variables for which the output is equal to 0. each term is a sum of all the variables of the expression.

in the spos form, a variable appears in its complemented form if it has a value of 1 in the combination, and it appears in un-complemented form if it has a value of 0 in the combination.

in the case of standard product of sums form, a term which contains each of the n variables of the function in either complemented or un-complemented form is called a maxterm. for a logical function in n variables, there could be at the most 2ⁿmaxterms. the product of maxterms of a logical expression whose value is 0 is called the standard product of sums form of the expression.

similar to the ssop form, we can obtain the standard product of sums form from the truth table of the logical expression by determining the product of all the sum terms that correspond to those combinations of variables for which the given logical expression (say f) has the value equal to 0.

also, the spos form of a logical expression can be obtained by using boolean algebra.

for example,

$$\mathrm{\mathit{f} \lgroup a,b,c \rgroup \: = \: \lgroup \bar{a} \: + \: b \rgroup \: + \: \lgroup a \: + \: \bar{c} \rgroup}$$

this is a logical expression in three variables, but it is expressed in pos form. we can convert this expression into spos form by using boolean algebra as follows.

$$\mathrm{\mathit{f} \lgroup a,b,c\rgroup \: = \: \lgroup \bar{a} \: + \: b \: + \: c \bar{c} \rgroup \: + \: \lgroup a \: + \: \bar{c} \: + \: b \bar{b} \rgroup}$$

$$\mathrm{\mathit{f} \lgroup a,b,c \rgroup \: = \: \lgroup \bar{a} \: + \: b \: + \: c \rgroup \lgroup \bar{a} \: + \: b \: + \: \bar{c} \rgroup \lgroup a \: + \: b \: + \: \bar{c} \rgroup \lgroup a \: + \: \bar{b} \: + \: \bar{c} \rgroup}$$

this is the standard product of sums (spos) form of the given logical expression. here, we can note that in the spos form, each sum term contains all the variables of the logic function either in complemented or un-complemented form.

what is karnaugh map?

in realization of digital electronic systems, the simplification of boolean expressions is one of the most crucial steps because it reduces the hardware complexity and cost of production. there are several tools and methods available for simplifying complex boolean expression. k-map or karnaugh map is one of such simplification methods. k-map was developed by maurice karnaugh in the year of 1953. it is a visual or graphical method used to simplify the boolean expressions.

k-map is one of the most efficient simplification tools when the number of variables in the boolean expression are less than or equal to four. however, for five, six, and more variables, the k-map becomes quite difficult.

the k-map or karnaugh map makes the use of two dimensional table for simplification of the boolean functions. the size of this table increases considerably with the increase in the number of variables in the boolean functions.

some typical examples of k-map of two variable, three variable, and four variables are shown in figure-1.

from figure-1, it is clear that the number of squares or cells in the karnaugh map depends on the number of variables in the expression.

if n is the number of variables in the given boolean function, then the corresponding karnaugh map (k-map) will have 2ⁿ squares or cells. for examples, if the number of variables in the boolean function is 3, then the corresponding k-map will have 8 (= 2³) cells.

structure of karnaugh map

all the karnaugh maps or k-maps have a generalized similar structure as shown in figure-1. a typical k-map has a table of certain cells. on the top-left corner of this table, a set of variables are represented as a, b, c, d. these variables are basically the input variables involved in the logical expression that requires to be simplified.

the values of these inputs variables in binary form are represented along their respective sides, i.e., on the top and left of the table.

from the above examples, it can be observed that the binary numbers along the top and left of the k-map are not in their normal binary order, instead they are in the gray code. the gray code is used to ensure that the two physically adjacent cells are actually adjacent. this makes the process of grouping easier during minimization of the boolean expression.

for providing simplicity in reading the k-map, each cell of the k-map is assigned a decimal number represented at the bottom-right corner of the cell. for example, in the three variable k-map (figure-1), the second cell of the k-map represents a bit pattern 001, hence this cell is represented by its decimal equivalent 1.

k-map simplification

the procedure of k-map or karnaugh map simplification is started with the entering the values of the variables, either in their sop (sum of products) form or in pos (product of sums) form, in the right k-map cells. after that we need to group the maximum number of 1s (in the case of sop form) or the maximum number of 0s (in the case of pos form). each of these groups must be in powers of 2 and must be carried on in decreasing order only.

once the grouping is done, each group has to be expressed in terms of combinations of input variables which are corresponding to the common binary values along the associated rows and columns. at last, all the combinations express the output expression of the boolean function.

advantages of karnaugh map

the following are the important advantages of the karnaugh map −

for simplifying boolean expression, the k-map does not require the knowledge of theorems of boolean algebra.
karnaugh map involves less number of steps in simplification process of logical expressions as compared to other simplification techniques.

limitations of karnaugh map

the following are the major limitations of the karnaugh map −

the most significant limitation of the karnaugh map is that it is only efficient when the boolean expression has less number of variables. it becomes quite complicated with the higher number of variables in the logical expression.
the simplification of a boolean function having more than or equal to five variables using k-map is quite complex.
it is very difficult to get equations correct with more than 5 variables using the k-map.

conclusion

the karnaugh map or k-map is an efficient tool for simplifying boolean expression up to 4 variables. it is an easy method for simplification of logic expression because it does not make the use of boolean algebra theorems. another advantage of k-map is that it is a visual method of simplification. however, the k-map becomes complex and inefficient when the variables in the logical expression are equal to or more than 5.

a k-map or karnaugh map is a graphical method that used for simplifying the complex algebraic expressions in boolean functions. this method avoid the use of complex theorems and equations manipulations. a k-map is basically a special form of a truth table that can easily map out the values of parameters and gives a simplified boolean expression.

k-map method is best suited for such boolean functions that have two to four variables. however, it can be used for boolean functions having five or six variables as well, but its process becomes more difficult with the increased number of variables in the function.

therefore, in practice, we mostly use two-variable k-map, three-variable k-map, and four-variable k-map. but, sometimes, the five-variable k-map and six-variable k-map are also used to derive the boolean expressions.

here, we will discuss the 3 variable k-map and its application to simplify a complex boolean function.

three-variable k-map

we can use the k-map to simplify a boolean function of three-variables. a boolean function in three variables (a, b, c) can be expressed in the standard sum of product (sop) form that can have total eight possible combinations, which are as follows −

$$\mathrm{(a'b'c'), (a'b'c), (a'bc'), (a'bc), (ab'c'), (ab'c), (abc'), (abc)}$$

we can designate each of these combinations by m₀, m₁, m₂, m₃, m₄, m₅, m₆, and m₇ respectively. each of these terms are called a min-term. in these combinations, a is called msb (most significant bit) and c is called lsb (least significant bit).

in terms of pos (product of sum) form, the eight possible combinations of the three variables boolean expression are as follows −

$$\mathrm{(a+b+c), (a+b+c'), (a+b'+c), (a+b'+c'), (a'+b+c), (a'+b+c'), (a'+b'+c), (a'+b'+c')}$$

each one of these combinations are often designated by m₀, m₁, m₂, m₃, m₄, m₅, m₆, and m₇ respectively. each of these terms is called a maxterm. similar to the minterm, a is called msb (most significant bit) and c is called lsb (least significant bit).

therefore, a three variable k-map has eight (2³) squares or cells, and each square on the k-map represents a minterm of a maxterm as shown in the following figure.

here, the small number on the bottom right corner of each cell indicates the minterm or maxterm designation.

the binary numbers along the top of the k-map indicates the condition of variables b and c for each column. the binary number along the left side of the map against each row represents the condition of the variable a for that row.

for example, the binary number of 10 on the top of the fourth column in the above figure indicates that the variable b appears in non-complimented form and the variable c appears in complimented form in all the minterms in that column. the binary number 0 on the left of the first row on the k-map indicates that the variable a appears in its complimented form in all the minterms, and the binary number 1 on the left of the second row on the k-map indicates that the variable a appears in its non-complimented form in all the minterms.

also, note that the binary numbers on top of the k-map are not in the normal binary order, but they are actually in the gray code. the use of gray code in k-map ensures that the two physically adjacent cells are actually adjacent which means their minterms or maxterms differs by one variable only.

numerical example

map the following three-variable boolean expression on k-map.

$$\mathrm{f \: = \: \overline{a} \: \overline{b} \: c \: + \: a \: \overline{b} \: c \: + \: \overline{a} \: b \: \overline{c} \: + \: a \: \overline{b} \: \overline{c} \: + \: a \: b \: c}$$

solution

in the given boolean expression, the minterms are −

$$\mathrm{\overline{a} \: \overline{b} \: c \: = \: 001; \: a \: \overline{b} \: c \: = \: 101; \: \overline{a} \: b \: \overline{c} \: = \: 010; \: a \: \overline{b} \: \overline{c} \: = \: 100; \: abc \: = \: 111}$$

therefore,

$$\mathrm{m_{1} \: = \: \overline{a} \: \overline{b} \: c \: = \: 001}$$

$$\mathrm{m_{5} \: = \: a \: \overline{b} \: c \: = \: 101}$$

$$\mathrm{m_{2} \: = \: \overline{a} \: b \: \overline{c} \: = \: 010}$$

$$\mathrm{m_{4} \: = \: a \: \overline{b} \: \overline{c} \: = \: 100}$$

$$\mathrm{m_{7} \: = \: abc \: = \: 111}$$

hence, the expression is given by,

$$\mathrm{f \: = \: \sum \: m (1, \: 5, \: 2, \: 4, \: 7)}$$

the k-map of this expression is shown in the following figure −

conclusion

from the above discussion, we may conclude that the three variable k-map is a graphical method used to simplify the complex three variable boolean function. a three-variable kmap has eight squares or cells.

several techniques have been developed to simplify a complex boolean expression into its simplest form. k-map or karnaugh map is one of such minimization or simplification techniques.

the k-map or karnaugh map is a graph or chart which composed of an arrangement of adjacent cells. where, each cell of the k-map represents a particular combination of variables in either sum or product form. the k-map can be used to simplify boolean functions involving any number of variables. but, the simplification of a boolean function using k-map becomes tedious for problems involving five or more variables. therefore, in actual practice, the k-map is limited to six variables.

the number of cells in a k-map depends upon the number of variables in the given boolean function. a k-map will have 2ⁿ cells or squares, where n is the number of variables in the boolean expression. therefore, for a two variable function, the k-map will have 2² = 4 cells, for a three variable boolean function, the k-map will have 2³ = 8 cells, and for four variable boolean function, the k-map will have 2⁴ = 16 cells, and so on.

here, we will discuss four variable k-map and will use it to simplify boolean functions in 4 variables.

four variable k-map

a four variable k-map is used to simplify a complex boolean expression in 4 variables. as we know, a four variable boolean expression can have 2⁴ = 16 possible combinations of variables.

for example, in sop (sum of products) form,

$$\mathrm{f(a,b,c,d) \: = \: \bar{a}\bar{b}\bar{c}\bar{d} \: + \: \bar{a}\bar{b}\bar{c}d \: + \: \bar{a}\bar{b}c\bar{d} \: + \: \dots \: + \: abcd}$$

the minterm representation of this expression is as follows,

$$\mathrm{f(a,b,c,d) \: = \: m_{0} \: + \: m_{1} \: + \: m_{2} \: + \: \dotso \: + \: m_{15}}$$

in pos (product of sums) form,

$$\mathrm{f(a,b,c,d) \: = \: (a \: + \: b \: + \: c \: + \: d)(a \: + \: b \: + \: c \: + \: \overline{d} )(a \: + \: b \: + \: \overline{c} \: + \: d) \: \dotso \: (\overline{a} \: + \: \overline{b} \: + \: \overline{c} \: + \: \overline{d})}$$

the maxterm representation of this expression is as,

$$\mathrm{f(a,b,c,d) \: = \: m_{0}\cdot m_{1}\cdot m_{2} \: \dotso \: m_{15}}$$

a 4 variable k-map has 16 cells, where each cell represents either a minterm or a maxterm of the function. the sop (sum of products) form and pos (product of sums) form of a four variable boolean expression is shown in figure 1.

here, the binary number designations of the columns and rows are in the gray code. this is known as adjacent ordering. in these k-maps, the binary numbers along the left side of the map indicate the conditions of variables a and b along any row, and the binary numbers along the top of the k-map indicate the conditions of the variables c and d along any column. the decimal numbers in the bottom right corners of the cells indicate the minterm or maxterm designation.

now, let us consider an example to illustrate the utilization of the 4 variable k-map for simplification of a boolean function.

example 1

simplify the following boolean expression using the 4-variable k-map.

$$\mathrm{f \lgroup a,b,c,d \rgroup \: = \: \sum m \lgroup 2,3,6,7,8,10,13,15 \rgroup}$$

solution

the sop k-map representation of the given boolean function is shown in figure 2.

explanation

the simplification of the function is done as per the following steps −

there are no isolated 1s in the k-map.

the minterm m2 can form a 4-square with m3, m6, and m7. make it and read it as −

$$\mathrm{\bar{a}c}()$$

the minterm m8 can form a 2-square with m10. make it and read it as −

$$\mathrm{ab\bar{d}}()$$

the minterm m13 can form a 2-square with m15. make it and read it as −

$$\mathrm{(a\bar{b}d)}$$

write all the product in sop form.

so the simplified sop expression is,

$$\mathrm{f(a,b,c,d) \: = \: \bar{a}c \: + \: a\bar{b}d \: + \: ab\bar{d}}$$

example 2

minimize the following boolean expression using the 4-variable k-map.

$$\mathrm{f(a,b,c,d) \: = \: \prod \: m(4,6,11,14,15)}$$

solution

the pos k-map representation of the given boolean function is shown in figure 3.

explanation

in minimization of the given function is done as per the following step −

there are no isolated zeros in the k-map.

the maxterm m4 can form a 2-squate with m6. make it and read it as −

$$\mathrm{(a \: + \: \bar{b} \: + \: d)}$$

the maxterm m11 can form a 2-square with m15. make it and read it as −

$$\mathrm{(\bar{a} \: + \: \bar{c} \: + \: \bar{d})}$$

now, only maxterm m₁₄ is left. m₁₄ can form 2-square with m₆ or m₁₅. if we make it with m15, then read it as −

$$\mathrm{(\bar{a} \: + \: \bar{b} \: + \: \bar{c})}$$

finally, write all the sum terms in pos form.

so, the reduced pos expression of the given boolean function is,

$$\mathrm{f(a,b,c,d) \: = \: (a \: + \: \bar{b} \: + \: d)(\bar{a} \: + \: \bar{c} \: + \: \bar{d})(\bar{a} \: + \: \bar{b} \: + \: \bar{c})}$$

numerical problems on k-map

q1. reduce the following boolean function using 4-variable k-map

$$\mathrm{f \lgroup a,b,c,d \rgroup \: = \: \sum m \lgroup 0,1,2,5,8,10,11,13,14,15 \rgroup }$$

q2. minimize the following boolean expression using 4-variable k-map.

$$\mathrm{f \lgroup a,b,c,d \rgroup \: = \: \prod \: m \lgroup 0,2,8,10,11,13,15 \rgroup}$$

conclusion

this is all about the 4 variable k-map and its application to minimize a boolean expression into its minimal form. from the above discussion, we can conclude that the 4-variable k-map is a graphical representation of a boolean expression involving 4 variables and is represented in standard sop or pos form. this is used to convert a standard sop or pos form, or minterm form or maxterm form of a 4-variable boolean expression into its minimal sop or pos form.

k-map or karnaugh map is a simplification technique used to minimize a given complex boolean function. k-map or karnaugh map is a graph or chart which is composed of an arrangement of adjacent cells, where each cell of the k-map represents a particular combination of variables in either sum or product form. the k-map can be used to simplify boolean functions involving any number of variables. but, the simplification of a boolean function using k-map becomes very complex for expressions involving five or more variables. therefore, in actual practice, the k-map is limited to six variables.

here, we will discuss five variable k-map and will use it to simplify boolean functions in 5 variables. so lets start with the introduction of 5 variable k-map.

five variable k-map

a five variable k-map is used to minimize a 5-variable boolean expression to its reduced form. the following are the important characteristics of a 5 variable k-map −

a five variable k-map have 32 (2⁵) cells or squares, and each cell of the k-map represents either a minterm or a maxterm of the boolean expression.

if the given boolean function is expressed in sop (sum of products) form, then the minterms of five variables boolean function are designated as m₀,m₁,m₂,m₃ ... m₃₁. where, m₀ is corresponding to $\mathrm{\lgroup \overline{a} \: \overline{b} \: \overline{c} \: \overline{d} \: \overline{e} \rgroup}$, m₁ is corresponding to $\mathrm{\lgroup \overline{a} \: \overline{b} \: \overline{c} \: \overline{d} e \rgroup}$, and m₃₁ is corresponding to $\mathrm{\lgroup abcde \rgroup}$.

on the other hand, if the 5 variable boolean function is expressed in pos (product of sums) form, then the maxterms of the function are designated as m₀, m₁, m₂, m₃₁.

where, m0 represents

$$\mathrm{\lgroup a \: + \: b \: + \: c \: + \: d \: + \: e \rgroup}$$

m₁ represents

$$\mathrm{\lgroup a \: + \: b \: + \: c \: + \: d \: + \: \overline{e} \rgroup}$$

m₃₁ represents

$$\mathrm{\lgroup \overline{a} \: + \: \overline{b} \: + \: \overline{c} \: + \: \overline{d} \: + \: \overline{e} \rgroup}$$.

the 32 cells of the five variable k-map are divided into two blocks of 16 cells each, which are arranged side by side. the left block represents minterms (or maxterms) from m₀ to m₁₅ (or m₀ to m₁₅. wheck, thck, th). in the left block, the first variable (let a) is a 0. the right block represents minterms (or maxterms) from m₁₆ to m₃₁ (or m₁₆ to m₃₁), in this block a is a 1.

in the five variable k-map, we can form 2-squares, 4-squares, 8-squares, 16-squares, or 32-squares by involving its two blocks. also, squares are considered adjacent in these two blocks, when one block superimposes on the top of another.

a five variable sop k-map is shown in figure 1.

a five variable pos k-map is represented in figure 2.

now, let us discuss some solved examples to understand the application of a 5 variable k map in reducing a given 5-variable boolean function in either sop form or pos form.

example 1

reduce the following 5 variable boolean function in sop form using the five variable k map.

$$\mathrm{f \lgroup a,b,c,d,e \rgroup \: = \: \sum \: m \lgroup 0,1,2,4,7,8,12,14,15,16,17,18,20,24,28,30,31 \rgroup }$$

solution

the sop k-map representation of the given sop boolean function is shown in figure 3.

five variable sop k-map boolean function

explanation

the minimization of the given 5 variable boolean function using the five variable k-map (figure 3) is done as per the following steps −

there are no isolated 1s in the k-map.

the minterm m₀ can form an 8-square with m₄, m₈, m₁₂, m₁₆, m₂₀, m₂₄, and m₂₈. so make it and read it as −

$$\mathrm{\lgroup \overline{d} \: \overline{e} \rgroup} $$

the minterms m₀, m₁, m₁₆, and m₁₇ form a 4-square. make it and read it as −

$$\mathrm{\lgroup \overline{b} \: \overline{c} \: \overline{d} \rgroup} $$

the minterms m₀, m₂, m₁₆, and m₁₈ form a 4-square. make it and read it as −

$$\mathrm{\lgroup \overline{b} \: \overline{c} \: \overline{e} \rgroup}$$

the minterms m₇ and m₁₅ form a 2-square. make it and read it as −

$$\mathrm{\lgroup \overline{a}cde \rgroup} $$

the minterms m₁₄, m₁₅, m₃₀ and m₃₁ form a 4-square. make it and read it as −

$$\mathrm{\lgroup bcd \rgroup} $$

finally, write all the product terms in sop form.

hence, the minimal sop expression of the given 5 variable boolean function is,

$$\mathrm{f(a,b,c,d,e) \ = \: \overline{a}cde \: + \: \overline{b} \: \overline{c} \: \overline{d} \: + \: \overline{b} \: \overline{c} \: \overline{e} \: + \: bcd \: + \: \overline{d} \: \overline{e}}$$

example 2

minimize the following 5 variable boolean function in pos form using the five variable k map.

$$\mathrm{f \lgroup a,b,c,d,e \rgroup \: = \: \prod \: m \lgroup 3,5,6,9,10,11,13,19,21,22,23,25,26,27,29 \rgroup}$$

solution

the pos k-map representation of the given pos boolean function is shown in figure 4.

five variable pos k-map boolean function

explanation

the minimization of the given 5 variable boolean function using the five variable k-map (figure-4) is done as per the following steps −

there are no isolated zeros in the k-map.

the maxterms m₉, m₁₃, m₂₅, and m₂₉ form a 4 square. make it and read it as −

$$\mathrm{\lgroup \overline{b} \: + \: d \: + \: \overline{e} \rgroup} $$

the maxterms m₃, m₁₁, m₁₉, and m₂₇ form a 4 square. make it and read it as −

$$\mathrm{\lgroup c \: + \: \overline{d} \: + \: \overline{e} \rgroup} $$

the maxterms m₅, m₁₃, m₂₁, and m₂₉ form a 4 square. make it and read it as −

$$\mathrm{\lgroup \overline{c} \: + \: d \: + \: \overline{e} \rgroup}$$

the maxterms m₆ and m₂₂ form a 2 square. make it and read it as −

$$\mathrm{\lgroup b \: + \: \overline{c} \: + \: \overline{d} \: + \: e \rgroup}$$

the maxterms m₁₀, m₁₁, m₂₆, and m₂₇ form 4 square. make it and read it as −

$$\mathrm{\lgroup \overline{b} \: + \: c \: + \: \overline{d} \rgroup}$$

the maxterms m₂₂ and m₂₃ form 2 square. make it and read it as −

$$\mathrm{\lgroup \overline{a} \: + \: b \: + \: \overline{c} \ + \: \overline{d} \rgroup}$$

finally, write all the sum terms in pos form.

therefore, the minimal pos expression of the given boolean function in five variables is,

$$\mathrm{f \lgroup a,b,c,d,e \rgroup \: = \: \lgroup \overline{b} \: + \: d \: + \: \overline{e} \rgroup \lgroup c \: + \: \overline{d} \: + \: \overline{e} \rgroup \lgroup \overline{c} \: + \: d \: + \: \overline{e} \rgroup \lgroup b \: + \: \overline{c} \: + \: \overline{d} \: + \: e \rgroup \lgroup \overline{b} \: + \: c \: + \: \overline{d} \rgroup \lgroup \overline{a} \: + \: b \: + \: \overline{c} \: + \: \overline{d} \rgroup}$$

numerical problems on k-map

try to solve the following numerical problems to get better command on the utilization of five variable k-map to reduce a boolean expression.

q1. reduce the following five variable boolean expression in sop form using k-map.

$$\mathrm{f \lgroup a,b,c,d,e \rgroup \: = \: \sum m \lgroup 0,3,4,6,8,10,11,12,15,17,18,22,25,26,27,30,31 \rgroup }$$

q2. reduce the following five variable boolean expression in pos form using k-map.

$$\mathrm{f \lgroup a,b,c,d,e \rgroup \: = \: \prod \: m\lgroup 0,1,2,4,6,7,9,10,11,13,15,16,18,19,25,26,28,29,31 \rgroup }$$

conclusion

this is all about the five variable k-map. from the above discussion, we can conclude that a five variable boolean function can be reduced to the minimal form using the 5 variable k-map. a five variable k-map has 32 squares or cells from 0 to 31. these 32 cells are arranged in two blocks 16 cells each. however, the split form of the 5 variable k-map into two blocks makes the use of it to minimize a boolean function slightly complex.

read this chapter to learn how you can use the k-map (karnaugh map) to reduce a boolean function in six variables. let's start with a brief introduction to karnaugh map (k-map).

karnaugh map (k-map)

the karnaugh map or k-map is a graphical method of reducing a boolean function to its minimal form. the k-map can be defined as a chart or a graph that is composed of an arrangement of adjacent squares or cells, where each cell represents a particular combination of variables of the boolean expression either in sum or product form. a typical 2 variable k-map is represented in figure-1.

in actual practice, we generally use a k-map upto 6 variables. however, k-map can be used for any number of variables, but for variables 5 or more, it becomes tedious.

now, let us discuss the six variable k-map and its application to reduce a boolean function to the minimal form.

six variable k-map

a six variable k-map is used to reduce a boolean expression of six variables (say a, b, c, d, e, f). it has 64 (2⁶) adjacent cells or squares. where, each cell represents a combination of variables of the function.

for a 6-variable boolean function in sop form, the possible combinations of the input variables are as follows −

$$\mathrm{\bar{a}\bar{b}\bar{c}\bar{d}\bar{e}\bar{f}, \: \bar{a}\bar{b}\bar{c}\bar{d}\bar{e}f, \: \bar{a}\bar{b}\bar{c}\bar{d}e\bar{f}, \: \dots \: abcdef}$$

the minterm designations of these combinations of variables are m₀, m₁, m₂ m₆₃ respectively.

similarly, for a 6-variables boolean function in pos form, the possible combinations of input variables are as follows −

$$\mathrm{\left ( a \: + \: b \: + \: c \: + \: d \: + \: e \: + \: f \right ), \: \left ( a \: + \: b \: + \: c \: + \: d \: + \: e \: + \: \bar{f} \right ), \: \left ( a \: + \: b \: + \: c \: + \: d \: + \: \bar{e} \: + \: f \right ), \: \dots \: \left ( \bar{a} \: + \: \bar{b} \: + \: \bar{c} \: + \: \bar{d} \: + \: \bar{e} \: + \: \bar{f} \right )}$$

the maxterm designations of these combinations of variables are m₀, m₁, m₂, ... m₆₃ respectively.

as already mentioned, the six variable k-map has 64 cells which are divided into 4-blocks of 16 squares each. each cell on the k-map represents a minterm or a maxterm. in the case of 6 variable k-map, the values of variables a and b remain the same for all minterms (or maxterms) in each block of 16 squares.

the 64 cells of a six variable k-map are divided into 4 blocks as follows −

block 1 − this is the top left block. this block represents minterms from m₀ to m₁₅, (or maxterms from m₀ to m₁₅). in this block, the variable a is a 0 and the variable b is also a 0.

block 2 − this is the top right block. this block represents minterms from m₁₆ to m₃₁, (or maxterms from m₁₆ to m₃₁). in this block, the variable a is a 0 and the variable b is a 1.

block 3 − this is the bottom left block. this block represents minterms from m₃₂ to m₄₇, (or maxterms from m₃₂ to m₄₇). in this block, the variable a is a 1 and the variable b is a 0.

block 4 − this is the bottom right block. this block represents minterms from m₄₈ to m₆₃, (or maxterms from m₄₈ to m₆₃). in this block, the variable a is a 1 and the variable b is also a 1.

while simplification, the 6-variable k-map may contain 2-squares, 4-squares, 8-squares, 16- squares, 32-squares, or a 64-square by involving all the four blocks of the map.

in a six variable k-map, when a block is superimposed on the top of another block, which is either above or below or beside of the first block, and the squares coincide with one another. then, the squares are considered adjacent in the two blocks. it is also important to note that the diagonal elements such as m₁₀ and m₅₈, m₁₅ and m₆₃, m₁₈ and m₃₄, m₂₉ and m₄₅ are not adjacent to each other.

a six variable sop k-map is represented in figure-2.

a six variable pos k-map is represented in figure-3.

now, let us understand the utilization of the six variable k-map for minimization of a six variable boolean function with the help of solved numerical examples.

example 1

minimize the following 6 variable boolean function using k-map.

$$\mathrm{f \: = \: \sum \: m(1, 3, 4, 5, 6, 9, 11, 12, 14, 15, 17, 19, 20, 21, 22, 23,25, 27, 28, 30, 33, 35, 36, 38, 41, 43, 44, 46, 49, 51, 52, 54, 57, 59, 60, 62)}$$

solution

the 6-variable sop k-map representation of the given boolean function is shown in figure-4.

six variable boolean function using k-map

the reduction of this function is done as per the following steps −

there are no isolated 1s in the k-map.

the minterm m₁ forms a 16-square with minterms m₃, m₉, m₁₁, m₁₇, m₁₉, m₂₅, m₂₇, m₃₃, m₃₅, m₄₁, m₄₃, m₄₉, m₅₁, m₅₇, and m₅₉. make it and read it as −

$$\mathrm{\bar{d}f}$$

the minterm m₄ forms a 16-square with minterms m₆, m₁₂, m₁₄, m₂₀, m₂₂, m₂₈, m₃₀, m₃₆, m₃₈, m₄₄, m₄₆, m₅₂, m₅₄, m₆₀, and m₆₂. make it and read it as −

$$\mathrm{\bar{f}d}$$

the minterm m₅ can form a 4-square with minterms m₄, m₂₀, and m₂₁, or with m₁, m₁₇, and m₂₁. we will make it with minterms m₄, m₂₀, and m₂₁, and read it as −

$$\mathrm{\bar{a}\bar{c}d\bar{e}}$$

the minterm m₂₁ forms a 4-square with minterms m₁₇, m₁₉, and m₂₃. make it and read it as −

$$\mathrm{\bar{a}b\bar{c}f}$$

the minterm m₁₅ can make a 2-square with the minterm m₁₁ or m₁₄. we will make it with m₁₄, and read it as −

$$\mathrm{\bar{a}\bar{b}cde}$$

write all the product terms in sop form.

therefore, the minimal sop expression is,

$$\mathrm{f \left ( a,b,c,d,e,f \right ) \: = \: \bar{d}f \: + \: d\bar{f} \: + \: \bar{a}\bar{c}d\bar{e} \: + \: \bar{a}b\bar{c}f \: + \: \bar{a}\bar{b}cde}$$

example 2

minimize the following six variable boolean function using k-map.

$$\mathrm{f \: = \: \pi \: m(0, 2, 7, 8, 10, 13, 16, 18, 24, 26, 29, 31,32, 34, 37, 39, 40, 42, 45, 47, 48, 50, 53, 55, 56, 58, 61, 63)}$$

solution

the 6-variable pos k-map representation of the given boolean function is shown in figure-5.

the reduction of this function is done as per the following steps −

there are no isolated 0s in the k-map.

the maxterm m₀ forms a 16-square with maxterms m₂, m₈, m₁₀, m₁₆, m₁₈, m₂₄, m₂₆, m₃₂, m₃₄, m₄₀, m₄₂, m₄₈, m₅₀, m₅₆, m₅₈. make it and read it as −

$$\mathrm{\left ( d \: + \: f \right )}$$

the maxterm m₃₇ forms an 8-square with maxterms m₃₉, m₄₅, m₄₇, m₅₃, m₅₅, m₆₁, and m₆₃. make it and read it as −

$$\mathrm{\left (\bar{a} \: + \: \bar{d} \: + \: \bar{f} \right )}$$

the maxterm m₁₃ makes a 4-square with maxterms m₂₉, m₄₅, and m₆₁. make it and read it as −

$$\mathrm{\left(\bar{c} \: + \: \bar{d} \: + \: e \: + \: \bar{f} \right )}$$

the maxterm m₃₁ makes a 4-square with m₂₉, m₆₁, and m₆₃. make it and read it as −

$$\mathrm{\left( \bar{b} \: + \: \bar{c} \: + \: \bar{d} \: + \: \bar{f} \right )}$$

the maxterm m₇ forms a 2-square with the maxterm m₃₉. make it and read it as −

$$\mathrm{\left( b \: + \: c \: + \: e \: + \: \bar{d} \: + \: \bar{e} \: + \: \bar{f} \right )}$$

write all the sum terms in pos form.

thus, the minimal pos expression for the given boolean function is,

$$\mathrm{f \left ( a,b,c,d,e,f \right ) \: = \: \left ( d \: + \: f \right )\left ( \bar{a} \: + \: \bar{d} \: + \: \bar{f} \right )\left( \bar{c} \: + \: \bar{d} \: + \: e \: + \: \bar{f} \right )\left( \bar{b} \: + \: \bar{c} \: + \: \bar{d} \: + \: \bar{f} \right )\left( b \: + \: c \: + \: e \: + \: \bar{d} \: + \: \bar{e} \: + \: \bar{f} \right )}$$

this is all about six variable k-map and its application in minimization of boolean functions. try solving the following tutorial problems to excel in the concept of six variable k-map and its application to reduce boolean expressions.

numerical problems on k-map

q. 1 − minimize the following six variable boolean function in sop form using k-map.

$$\mathrm{f \left ( a,b,c,d,e,f \right ) \: = \: \sum m(1, 3, 5, 7, 9, 10, 11, 12, 14, 16, 17, 19, 20, 22, 24, 25, 26, 31, 32,34, 36, 37, 39, 40, 42, 45, 49, 50, 53, 54, 57, 60, 61, 63)} $$

q. 2 − minimize the following six variable boolean function in pos form using k-map.

$$\mathrm{f \left ( a,b,c,d,e,f \right ) \: = \: \pi m(0, 1, 3, 4, 5, 6, 8, 9, 10, 12, 14, 15, 17, 20, 21, 22, 25, 26, 27,29, 30, 32, 33, 35, 36, 37, 39, 40, 41, 42, 45, 47, 48, 50, 52, 53, 55, 56, 58, 59, 60, 62 )}$$

k-map or karnaugh map is a graphical method of simplifying boolean expression. a k-map composed of an arrangement of adjacent squares or cells, where each cell represent a particular combination of variables in sum or product form.

in the k-map method, there is a useful condition namely, dont care condition, which helps in simplifying a boolean function. the dont care condition makes the grouping of variables in k-map easy. in this tutorial, we will understand the "dont care" concept in k-map reduction with the help of solved examples.

sometimes, in a boolean expression for certain input combinations, the value of the output is not specified either due to invalid input combinations or due to the precise value of output is of no importance. these input combinations for which the values of the boolean function are not specified are called dont care combinations. dont care combinations are also referred to as optional combinations. in k-map, dont care combinations are represented by "x" or "d" or "".

for example, in 8421 binary code, the binary combination 1010, 1011, 1100, 1101, 1110, and 1111 are the invalid terms and their corresponding outputs are dont care combinations. similarly, in excess-3 code, the combinations 0000, 0001, 0010, 1101, 1110, and 1111 do not occur, hence these are called dont care combinations.

when we deal with sop (sum of products) k-map, each dont care term is treated as a 1, if it helps in reduction of the expression, otherwise it is considered as a 0 and left alone.

on the other hand, when we are using pos (product of sums) k-map, each dont care term is considered as a 0, if it is helpful in reduction of the expression, otherwise it is treated as a 1 and left alone.

also, we can convert a standard sum of products (ssop) expression with dont care terms into a standard product of sums (spos) expression by keeping the dont care terms as they are, and writing the missing minterms of the ssop form as the maxterms of the spos form.

similarly, we can convert a standard product of sums (spos) expression with dont care terms into a standard sum of products (ssop) expression by keeping the dont care terms of the spos expression as they are, and writing the missing maxterms of the spos expression as the minterms of the ssop expression.

now, let us discuss some solved examples to understand the dont care condition in k-map.

example 1

minimize the following 4-variable boolean expression in sop form using k-map.

$$\mathrm{\mathit{f}\lgroup a,b,c,d\rgroup=\sum m \lgroup 0,1,4,5,6,10,13\rgroup +d \lgroup 2,3 \rgroup}$$

solution

the sop k-map representation of the given boolean function is shown in figure 1.

as we can see in the given expression, there are two dont care terms which are denoted by x on the k-map.

explanation

the reduction of the expression is done as per the following steps −

the minterms m₀, m₁, m₄ and m₅ form a 4-square. make it and read it as $\mathrm{\lgroup \bar{a} \: \bar{c}\rgroup}$.
the minterms m₁₀ and m₁₁ form a 4-sqaure with two dont care terms m₂ and m₃. make it and read it as $\mathrm{\bar{b}c}$.
the minterms m₀, m₄, m₆ and the dont care term m₂ together form a 4-square. make it and read it as $\mathrm{\bar{a} \: \bar{d}}$.
the minterms m₅ and m₁₃ form a 2-square. make it and read it as $\mathrm{b\bar{c}d}$.
finally, write all the product terms in sop form.

therefore, the minimal boolean expression is,

$$\mathrm{\mathit{f} \lgroup a,b,c,d \rgroup \: = \: \bar{a} \: \bar{c} \: + \: \bar{b}c \: + \: \bar{a} \: \bar{d} \: + \: b \bar{c}d}$$

example 2

minimize the following 4-variable boolean expression in pos form using k map.

$$\mathrm{\mathit{f} \lgroup a,b,c,d \rgroup \: = \: \prod m \lgroup 1,5,6,12,13,14 \rgroup \: + \: d \lgroup 2,4 \rgroup}$$

solution

the pos k-map representation of the given boolean function is shown in figure-2.

there are two dont care terms in the expression which are represented by x on the k-map.

explanation

the reduction of the given function is done as per the following steps −

the maxterms m₅, m₁₂ and m₁₃ and dont care term m₄ form a 4-square. make it and read it as $\mathrm{\bar{b} \: + \: c}$.
the maxterms m₆, m₁₂, and m₁₄ and dont care term m₄ form a 4-square. make it and read it as $\mathrm{\bar{b} \: + \: d}$.
the maxterms m₁ and m₅ form a 2-square. make it and read it as $\mathrm{a \: + \: c \: + \: \bar{d}}$
write all the sum terms in pos form.

therefore, the minimal boolean expression is,

$$\mathrm{\mathit{f} \lgroup a,b,c,d \rgroup \: = \: \lgroup \bar{b} \: + \: c \rgroup \: + \: \lgroup \bar{b} \: + \: d \rgroup \: + \: \lgroup a \: + \: c \: + \: \bar{d} \rgroup}$$

conclusion

this is all about dont care conditions in k-maps. as we discussed in the above sections of this tutorial, that the dont care condition is a significant and powerful concept that helps in minimization of boolean function using k-map.

in this chapter, we will discuss the minimization of boolean expressions using a tabular method also known as quine-mccluskey method.

the quine-mccluskey method is more beneficial in minimization of boolean functions of more than six variables. this minimization technique overcomes the issues associated with k-map for more than six variables.

another major advantage of quine-mccluskey method is that it is equally suitable both hand computation and machine computation, as it is programmable.

theory of quine-mccluskey method

the quine-mccluskey method is a systematic technique of minimizing complex boolean expressions. it becomes a suitable method to perform minimization of boolean expressions of large number of variables. it is also known as tabular method.

this minimization technique is based on the repeated use of the combining theorem (i.e., $\mathrm{xa \: + \: x\bar{a} \: = \: x}$, where x is a set of literals) on all adjacent pairs of terms. this process gives a set of all prime implicants, from which we can select a minimal sum.

quine-mccluskey method procedure

the step-by-step procedure for minimizing a boolean function by using the quine mccluskey method is explained below −

step 1 − list all the minterms of the given boolean expression.

step 2 − group the minterms. in this step, we arrange all the minterms in groups according to the number of 1s in their binary form. for example, arrange all the minterms with no 1s together, all the minterms with only one 1s together, and so on. the number of 1s in a minterm is called the index of the minterm. write these grouped minterms in the column 1 of the table.

step 3 − combine minterms. in this step, compare each minterm of the lowest index group with every minterm in the succeeding group. whenever possible, combine two minterms in adjacent groups that differ by only 1-bit and replace the differing bit by a dash (-). this represents a dont care condition. also, place a check mark () in front of the every minterm that has been combined with at least one minterm. repeat this process until all possible minterm combinations are made. write all the combined minterms in the column 2 of the table.

step 4 − compare and combine the minterms generated in the above step in the same manner. in this step, we combine two minterms which differ by only 1-bit and whose dashes are in the same position. we cannot combine two minterms having dashes in different positions.

write the newly generated terms in the column 3 and put a check mark () next to each term that has been combined in the column 2. continue this process with terms in column 3, 4, and so on until no further combination is possible. at the end, the terms that are not combined are called the prime implicants.

step 5 − list all the prime implicants and create a prime implicant chart. if there is any dont care, it should not appear in the prime implicant chart.

step 6 − select the essential prime implicants which are the prime implicants that cover a minterm which is not covered by any other prime implicant.

step 7 − combine the essential prime implicants to obtain the final minimized expression.

important terms related quine-mccluskey method

in the quine-mccluskey method of boolean expression minimization, several terms are used to convey information. some key terms related to the quine-mccluskey method are defined below −

minterm − a minterm is a combination of boolean variables that has 1 for true value and 0 for false value.

maxterm − a maxterm is a combination of boolean variables in which true values are designated by 0s and false values are designated by 1s.

index − the number of 1s in a minterm is called its index.

prime implicant − a minterm that cannot be combined with any other minterm is called a prime implicant.

essential prime implicant − a prime implicant that covers at least one minterm which is not covered by any other prime implicant is called an essential prime implicant.

prime implicant chart − the graphical representation showing the relationship between the prime implicants and the minterms of the boolean expression is called the prime implicant chart.

dont care condition − a dont care condition is a bit or variable that can be ignored during minimization of the function. in quine-mccluskey method, it is represented by a dash (-).

these are some important terms essential to work with the quine-mccluskey method.

let us now understand the application of quine-mccluskey method to minimize a boolean function through an example.

example based on quine-mccluskey method

using the quine-mccluskey technique minimize the following boolean function.

$$\mathrm{f(a, b,c,d) \: = \: \sum \: m(0,1,5,7,10,14)}$$

solution

the minimization of given boolean function using the quine-mccluskey method is explained below.

step 1 − grouping the given minterms in terms of number of 1s in ascending order and writing their binary form in column 1.

column 1
index	min term	binary form
index	min term	a	b	c	d
i0	0	0	0	0	0
i1	1	0	0	0	1
i2	5	0	1	0	1
i2	10	1	0	1	0
i3	7	0	1	1	1
i3	14	1	1	1	0

step 2 − comparing and combining minterms of the column 1.

column 1						column 2
index	min term	binary form					pairs	a	b	c	d
index	min term	a	b	c	d		pairs	a	b	c	d
i0	0	0	0	0	0	✓	0, 1 (1)	0	0	0	-	p
i1	1	0	0	0	1	✓	0, 1 (1)	0	0	0	-	p
i2	5	0	1	0	1	✓	1, 5 (4)	0	−	0	1	q
i2	10	1	0	1	0	✓	5, 7 (2)	0	1	−	1	r
i3	7	0	1	1	1	✓	5, 7 (2)	0	1	−	1	r
i3	14	1	1	1	0	✓	10, 14 (4)	1	−	1	0	s

we can see there is no term that can be combined with any other term in the column 2 between two adjacent groups. thus, all of them are prime implicants.

step 3 − creating the prime implicant chart.

pi	minterms	0	1	5	7	10	14
p	0, 1 (1)	x	x
q	1, 5 (4)		x	x
r	5, 7 (2)			x	x
s	10, 14 (4)					x	x

we can see from the prime implicant chart that the minterms m10 and m14 are covered by s only. hence, s is an essential prime implicant. it can also be observed that the remaining minterms of the function are covered by the minimal set of prime implicants p and r.

therefore, the minimal expression will be,

$$\mathrm{f_{min} \: = \: p \: + \: r \: + \: s \: = \: (000 \: − \: ) \: + \: (01 \: − \: 1) \: + \:(1 \: − \: 10)}$$

$$\mathrm{\rightarrow f_{min} \: = \: \overline{abc} \: + \: \overline{a}bd \: + \: ac\overline{d}}$$

this is minimal boolean expression for the given boolean function and it can be realized using and, or, and not gates.

advantages of quine-mccluskey method

the quine-mccluskey method offers several advantages over other minimization techniques such as karnaugh map. some of the key advantages of the quine-mccluskey method are listed below −

the quine-mccluskey method provides a systematic minimization process to find a minimal version of a complex boolean expression.
it can be applied to boolean functions of large number of variables where, the k-map technique becomes impractical.
it is suitable for both hand computation and computerized computation.
the quine-mccluskey method is based on a systematic algorithm that helps to reduce human errors.
it can also be applied to boolean functions with dont care conditions, i.e., incomplete boolean functions.

disadvantages of quine-mccluskey method

however, the quine-mccluskey method is a powerful simplification technique to minimize boolean functions having several advantages over other minimization techniques.

but, it also has certain disadvantages, some of which are listed below −

the primary disadvantage of the quine-mccluskey method is computational complexity. it is because, we have to check all the possible combinations of minterms.
although the quine-mccluskey method is better than k-map for large number of variables. but it also becomes impractical for vary large number of variables, typically more than 7 variables.
the quine-mccluskey method involves extensive manual computation that makes it tedious and prone to human error.
the quine-mccluskey method is not much effective for certain types of boolean functions.
as the quine mccluskey method involves an algorithmic approach for minimization rather than graphical approach. this makes it less intuitive.

applications of quine-mccluskey method

the quine-mccluskey method is one of the most effective minimization techniques in boolean algebra. it provides a systematic approach to minimized complex boolean functions of large number of variables. some major applications of the quine-mccluskey method are given below −

quine-mccluskey method is used to design and optimize digital circuits and systems. it helps reducing the number of logic gates used in the digital circuits.
it is also used in computer programming to optimize conditional logics for better efficiency and faster speed.
in digital signal processing, the quine-mccluskey method is used to simplify boolean expressions to develop efficient processing algorithms.
quine-mccluskey method is used to design efficient state machine.

conclusion

in conclusion, the quine-mccluskey method is a systematic and algorithmic approach for simplifying complex boolean expressions. it is an effective minimization technique for boolean functions of large number of variables.

the greatest advantage of the quine-mccluskey method is that it supports both hand computation and machine computation, i.e., it is programmable. however, this method involves relatively complex computation which makes it tedious.

any boolean function or logical expression can be expressed in either canonical/standard sum of products form or canonical/standard product of sums form. the standard sum of products form of a logical expression contains different product terms which are added together, and each product term is referred to as a minterm. on the other hand, the standard product of sums form of a logical expression contains different sum terms which are multiplied together, and each sum term is called a maxterm. in this article, we will discuss about the minterm and max terms.

what is minterm?

when a boolean function or logical expression is expressed in the ssop (standard sum of product) form or canonical form, then each term of the expression is called a minterm.

in other words, a product term of a logical expression in n variables, which contains each of the n variables in its either complemented or un-complemented form is called a minterm.

a minterm is often represented as mi, where, i is an integer in between 0 and 2^(n-1). here, "n" is the number of variables in the expression. therefore, minterms can be denoted as m₀, m₁, m₂,m₃,... here, the suffixes the decimal codes of the combinations of variables.

in a minterm, a variable will appear in its complemented form if its value is equal to 0. and, the variable will appear in its un-complimented form if its value is equal to 1.

now, let us consider some example to understand how a logical expression is expressed in minterms.

for a logical expression in 2-variables (a and b), the possible minterms are,

$$\mathrm{m_{0} \: = \: \overline{a} \: \overline{b}}$$

$$\mathrm{m_{1} \: = \: \overline{a}b}$$

$$\mathrm{m_{2} \: = \: a\overline{b}}$$

$$\mathrm{m_{3} \: = \: ab}$$

for a logical expression in 3-variables (a, b, and c), the possible minterms are,

$$\mathrm{m_{0} \: = \: \overline{a} \: \overline{b} \: \overline{c}}$$

$$\mathrm{m_{1} \: = \: \overline{a} \: \overline{b}c}$$

$$\mathrm{m_{2} \: = \: \overline{a}b \: \overline{c}}$$

$$\mathrm{m_{3} \: = \: \overline{a}bc}$$

$$\mathrm{m_{4} \: = \: a\overline{b} \: \overline{c}}$$

$$\mathrm{m_{5} \: = \: a\overline{b}c}$$

$$\mathrm{m_{6} \: = \: ab\overline{c}}$$

$$\mathrm{m_{7} \: = \: abc}$$

here, we can see that a logical function in two variables has four (2² = 4) minterms, and the logical function in 3-variables has eight (2³ = 8) minterms. the variable in complemented form (represented with a bar over the variable) has a value equal to 0 and the variable in un-complemented form has a value equal to 1.

what is maxterm?

when a boolean function or logical expression is expressed in the spos (standard product of sum) form or canonical form, then each term of the expression is called a maxterm.

in other words, a sum term of a logical expression in n variables, which contains each of the "n" variables in its either complemented or un-complemented form is called a maxterm.

the maxterm is often represented by mi, where "i" is an integer between 0 and 2^(n-1). here, "n" is the total number of variable in the logical expression. therefore, maxterms of a logical expression can be denoted as m₀, m₁, m₂, ... where the suffixes represent their decimal codes of the combinations.

in the case of maxterms, a variable will be written in its complemented form if its value is equal to 1, and the variable will be written in its un-complemented form if its value is equal to 0.

now, let us know how we can express a logical function in the form of maxterms.

for a boolean function in 2 variables (a and b), the possible maxterms are,

$$\mathrm{m_{0} \: = \: \lgroup a \: + \: b \rgroup}$$

$$\mathrm{m_{1} \: = \: \lgroup a \: + \: \overline{b} \rgroup}$$

$$\mathrm{m_{2} \: = \: \lgroup \overline{a} \: + \: b \rgroup}$$

$$\mathrm{m_{3} \: = \: \lgroup \overline{a} \: + \: \overline{b} \rgroup}$$

for a boolean expression in 3 variables (a, b, c), the possible maxterms are,

$$\mathrm{m_{0} \: = \: \lgroup a \: + \: b \: + \: c \rgroup}$$

$$\mathrm{m_{1} \: = \: \lgroup a \: + \: b \: + \: \overline{c} \rgroup}$$

$$\mathrm{m_{2} \: = \: \lgroup a \: + \: \overline{b} \: + \: c \rgroup}$$

$$\mathrm{m_{3} \: = \: \lgroup a \: + \: \overline{b} \: + \: \overline{c} \rgroup}$$

$$\mathrm{m_{4} \: = \: \lgroup \overline{a} \: + \: b \: + \: c \rgroup}$$

$$\mathrm{m_{5} \: = \: \lgroup \overline{a} \: + \: b \: + \: \overline{c} \rgroup}$$

$$\mathrm{m_{6} \: = \: \lgroup \overline{a} \: + \: \overline{b} \: + \: c \rgroup}$$

$$\mathrm{m_{7} \: = \: \lgroup \overline{a} \: + \: \overline{b} \: + \: \overline{c} \rgroup}$$

here, from these two logical expressions in 2-variables and 3-variables respectively, we can see that a logical function in two variables has four (2² = 4) maxterms, and the logical function in 3-variables has eight (2³ = 8) maxterms. in this case, the variable in un-complemented form (represented with a bar over the variable) has a value equal to 0 and the variable in complemented form has a value equal to 1.

conclusion

this is all about minterms and maxterms in boolean algebra. from the above discussion, we may conclude that a minterm is a product term of a logical expression, when the expression is represented in its standard sum of product (ssop) form. on the other hand, a maxterm is a sum term of a logical expression, where the logical expression is expressed in the standard product of sums (spos) form.

the common point about both minterm and maxterm is that they contain each of the "n" variables of the logical function.

we will get four boolean product terms by combining two variables x and y with logical and operation. these boolean product terms are called as min terms or standard product terms. the min terms are x'y', x'y, xy' and xy.

similarly, we will get four boolean sum terms by combining two variables x and y with logical or operation. these boolean sum terms are called as max terms or standard sum terms. the max terms are x + y, x + y', x' + y and x' + y.

the following table shows the representation of min terms and max terms for 2 variables.

x	y	min terms	max terms
0	0	m₀ = xy	m₀ = x + y
0	1	m₁ = xy	m₁ = x + y
1	0	m₂ = xy	m₂ = x + y
1	1	m₃ = xy	m₃ = x + y

if the binary variable is '0', then it is represented as complement of variable in min term and as the variable itself in max term. similarly, if the binary variable is '1', then it is represented as complement of variable in max term and as the variable itself in min term.

from the above table, we can easily notice that min terms and max terms are complement of each other. if there are 'n' boolean variables, then there will be 2ⁿ min terms and 2ⁿ max terms.

canonical sop and pos forms

a truth table consists of a set of inputs and output(s). if there are n input variables, then there will be 2ⁿ possible combinations with zeros and ones. so the value of each output variable depends on the combination of input variables. so, each output variable will have 1 for some combination of input variables and 0 for some other combination of input variables.

therefore, we can express each output variable in following two ways.

canonical sop form
canonical pos form

canonical sop form

canonical sop form means canonical sum of products form. in this form, each product term contains all literals. so, these product terms are nothing but the min terms. hence, canonical sop form is also called as sum of min terms form.

first, identify the min terms for which, the output variable is one and then do the logical or of those min terms in order to get the boolean expression (function) corresponding to that output variable. this boolean function will be in the form of sum of min terms.

follow the same procedure for other output variables also, if there is more than one output variable.

example

consider the following truth table.

inputs		output
p	q	r	f
0	0	0	0
0	0	1	0
0	1	0	0
0	1	1	1
1	0	0	0
1	0	1	1
1	1	0	1
1	1	1	1

here, the output (f) is '1' for four combinations of inputs. the corresponding min terms are p'qr, pq'r, pqr', pqr. by doing logical or of these four min terms, we will get the boolean function of output (f).

therefore, the boolean function of output is, f = p'qr + pq'r + pqr' + pqr. this is the canonical sop form of output, f. we can also represent this function in following two notations.

$$\mathrm{f \: = \: m_{3} \: + \: m_{5} \: + \: m_{6} \: + \: m_{7}}$$

$$\mathrm{f \: = \: \sum \: m\left ( 3, \:5, \:6, \:7 \right )}$$

in one equation, we represented the function as sum of respective min terms. in other equation, we used the symbol for summation of those min terms.

canonical pos form

canonical pos form means canonical product of sums form. in this form, each sum term contains all literals. so, these sum terms are nothing but the max terms. hence, canonical pos form is also called as product of max terms form.

first, identify the max terms for which, the output variable is zero and then do the logical and of those max terms in order to get the boolean expression (function) corresponding to that output variable. this boolean function will be in the form of product of max terms.

follow the same procedure for other output variables also, if there is more than one output variable.

example

consider the same truth table of previous example. here, the output (f) is '0' for four combinations of inputs. the corresponding max terms are p + q + r, p + q + r', p + q' + r, p' + q + r. by doing logical and of these four max terms, we will get the boolean function of output (f).

therefore, the boolean function of output is, f = (p + q + r)·(p + q + r')·(p + q' + r)·(p' + q + r). this is the canonical pos form of output, f. we can also represent this function in following two notations.

$$\mathrm{f \: = \: m_{0}\cdot m_{1} \cdot m_{2} \cdot m_{4}}$$

$$\mathrm{f \: = \: \prod m\left ( 0, \: 1, \: 2, \: 4 \right )}$$

in one equation, we represented the function as product of respective max terms. in other equation, we used the symbol for multiplication of those max terms.

the boolean function, f = (p + q + r)·(p + q + r)·(p + q + r)·(p + q + r) is the dual of the boolean function, f = p'qr + pq'r + pqr' + pqr.

therefore, both canonical sop and canonical pos forms are dual to each other. functionally, these two forms are same. based on the requirement, we can use one of these two forms.

standard sop and pos forms

we discussed two canonical forms of representing the boolean output(s). similarly, there are two standard forms of representing the boolean output(s). these are the simplified version of canonical forms.

standard sop form
standard pos form

we will discuss about logic gates in later chapters. the main advantage of standard forms is that the number of inputs applied to logic gates can be minimized. sometimes, there will be reduction in the total number of logic gates required.

standard sop form

standard sop form means standard sum of products form. in this form, each product term need not contain all literals. so, the product terms may or may not be the min terms. therefore, the standard sop form is the simplified form of canonical sop form.

we will get standard sop form of output variable in two steps.

get the canonical sop form of output variable
simplify the above boolean function, which is in canonical sop form.

follow the same procedure for other output variables also, if there is more than one output variable. sometimes, it may not possible to simplify the canonical sop form. in that case, both canonical and standard sop forms are same.

example

convert the following boolean function into standard sop form.

$$\mathrm{f \: = \: p'qr \: + \: pq'r \: + \: pqr' \: + \: pqr}$$

the given boolean function is in canonical sop form. now, we have to simplify this boolean function in order to get standard sop form.

step 1 − use the boolean postulate, x + x = x. that means, the logical or operation with any boolean variable n' times will be equal to the same variable. so, we can write the last term pqr two more times.

$$\mathrm{\rightarrow \: f \: = \: p'qr \: + \: pq'r \: + \: pqr' \: + \: pqr \: + \: pqr \: + \: pqr}$$

step 2 − use distributive law for 1^st and 4^th terms, 2^nd and 5^th terms, 3^rd and 6^th terms.

$$\mathrm{\rightarrow \: f \: = \: qr(p' + p) \: + \: pr(q' + q) \: + \: pq(r' + r)}$$

step 3 − use boolean postulate, x + x' = 1 for simplifying the terms present in each parenthesis.

$$\mathrm{\rightarrow \: f \: = \: qr(1) \: + \: pr(1) \: + \: pq(1)}$$

step 4 − use boolean postulate, x.1 = x for simplifying above three terms.

$$\mathrm{\rightarrow \: f \: = \: qr \: + \: pr \: + \: pq}$$

$$\mathrm{\rightarrow \: f \: = \: pq \: + \: qr \: + \: pr}$$

this is the simplified boolean function. therefore, the standard sop form corresponding to given canonical sop form is f = pq + qr + pr

standard pos form

standard pos form means standard product of sums form. in this form, each sum term need not contain all literals. so, the sum terms may or may not be the max terms. therefore, the standard pos form is the simplified form of canonical pos form.

we will get standard pos form of output variable in two steps.

get the canonical pos form of output variable
simplify the above boolean function, which is in canonical pos form.

follow the same procedure for other output variables also, if there is more than one output variable. sometimes, it may not possible to simplify the canonical pos form. in that case, both canonical and standard pos forms are same.

example

convert the following boolean function into standard pos form.

$$\mathrm{f \: = \: (p + q + r)\cdot(p + q + r')\cdot(p + q' + r)\cdot(p' + q + r)}$$

the given boolean function is in canonical pos form. now, we have to simplify this boolean function in order to get standard pos form.

step 1 − use the boolean postulate, x · x = x. that means, the logical and operation with any boolean variable n' times will be equal to the same variable. so, we can write the first term p+q+r two more times.

$$\mathrm{\rightarrow \: f \: = \: (p + q + r)\cdot(p + q + r)\cdot(p + q + r)\cdot(p + q + r')\cdot(p +q' + r)\cdot(p' + q + r)}$$

step 2 − use distributive law, x + (y · z) = (x + y)·(x + z) for 1^st and 4^th parenthesis, 2^nd and 5^th parenthesis, 3^rd and 6^th parenthesis.

$$\mathrm{\rightarrow \: f \: = \: (p + q + rr')\cdot(p + r + qq')\cdot(q + r + pp')}$$

step 3 − use boolean postulate, x.x'=0 for simplifying the terms present in each parenthesis.

$$\mathrm{\rightarrow \: f \: = \: (p + q + 0)\cdot(p + r + 0)\cdot(q + r + 0)}$$

step 4 − use boolean postulate, x + 0 = x for simplifying the terms present in each parenthesis

$$\mathrm{\rightarrow \: f \: = \: (p + q)\cdot(p + r)\cdot(q + r)}$$

$$\mathrm{\rightarrow \: f \: = \: (p + q)\cdot(q + r)\cdot(p + r)}$$

this is the simplified boolean function. therefore, the standard pos form corresponding to given canonical pos form is f = (p + q)·(q + r)·(p + r). this is the dual of the boolean function, f = pq + qr + pr.

therefore, both standard sop and standard pos forms are dual to each other.

the k-map or karnaugh map is a systematic method of simplifying a complex boolean function or expression. the k-map is basically a graph or a chart which consists of a certain number of adjacent cells. each cell represents a particular combination of variables in either sum or product form.

however, we can use the k-map for simplifying a boolean function in any number of variables, but it becomes tedious for functions involving five or more variables. in actual practice, we usually use k-map for simplification of boolean functions in upto six variables.

a boolean function in n variables can have 2ⁿ possible combinations of product terms in sum of products (sop) form, or 2ⁿ possible combinations of sum terms in product of sums (pos) form.

therefore, for a boolean function in 2 variables, the k-map will have 2² = 4 cells, for a function in 3 variables, it will have 2³ = 8 cells, and so on.

a boolean function can be expressed in two canonical or standard form namely ssop (standard sum of products) form and spos (standard product of sums) form.

a ssop form is one in which a boolean function is expressed as a sum of product terms, where each term of the expression contains all the variables of the function in either complemented or un-complemented form. each product term of the logic expression in ssop form is referred to as a minterm.

for example,

$$\mathrm{y \: = \: ab \: + \: \overline{a}b}$$

here, y is a boolean function in two variables a and b. the terms ab and ab' are the minterms of the function.

in the spos form, a boolean function is expressed as a product of sum terms, where each sum term, called maxterm, contains all the variables of the function in either complemented or non-complemented form.

for example,

$$\mathrm{y \: = \: \lgroup a \: + \: b\rgroup \: .\: \lgroup \overline{a} \: + \: b \rgroup}$$

here, y is a boolean function in two variables a and b, and the terms (a+b) and (a'+b) are the two maxterms of the function.

this article is primarily meant for explaining how to represent a boolean function in max term form on a k-map. so, let us discuss the maxterm representation or plotting zeros on k map.

plotting zeros (maxterm representation)

as we already discussed that each sum term in a standard pos form expression is called a maxterm. a maxterm is denoted by the uppercase letter m with a subscript which denotes the decimal designation of that maxterm.

for representing a standard pos expression on to the k-map, zeros are plotted in the cells corresponding to the maxterms which are represented in the expression, and no entries are made in the cells corresponding to the maxterms which are not present in the expression.

now, for better understanding of the concept of plotting zeros or maxterm representation, let us discuss some solved examples.

example 1

plot the following 2 variable boolean expression on the k-map.

$$\mathrm{y \: = \: \lgroup a \: + \: b \rgroup\lgroup a \: + \: \overline{b} \rgroup\lgroup \overline{a} \:+ \: b \rgroup}$$

solution

the given boolean expression in terms of maxterms can be represented as,

$$\mathrm{y \: = \: m_{3} \cdot m_{2} \cdot m_{1} \: = \: \prod m \lgroup 0, \: 1, \: 2 \rgroup}$$

the maxterm representation of this function on the k-map is shown in figure-1.

example 2

plot the following 3 variables boolean function on the k-map.

$$\mathrm{y \: = \: \lgroup a \: + \: b \: + \: c \rgroup\lgroup \overline{a} \: + \: \overline{b} \: + \: c\rgroup\lgroup a \: + \: b \: + \: \overline{c}\rgroup\lgroup \overline{a} \: + \: b \: + \: \overline{c} \rgroup\lgroup \overline{a} \: + \: \overline{b} \: + \: \overline{c}\rgroup}$$

solution

the given boolean function in terms of maxterms can be represented as,

$$\mathrm{y \: = \: m_{0} \cdot m_{1}\cdot m_{5} \cdot m_{6} \cdot m_{7} \: = \: \prod m \lgroup 0, \: 1, \: 5, \: 6, \: 7 \rgroup}$$

the maxterm representation of this function on the k-map is shown in figure 2.

hence, this is all about plotting zeros or maxterm representation of boolean expression on the k-map.

tutorial problems

try to solve the following tutorial problems to understand the concept more clearly.

q1. plot the following boolean expression in maxterm representation on the k-map.

$$\mathrm{f( a, \: b) \: = \: (a \: + \: b)\cdot(\overline{a} \: + \: b).(\overline{a} \: + \: \overline{b})}$$

q2. plot the following 3 variable boolean function in maxterm representation on the k map.

$$\mathrm{f(a, \: b, \: c) \: = \: (a \: + \: b \: + \: \overline{c})\cdot(a \: + \: \overline{b} \: + \: c)\cdot( \overline{a} \: + \: \overline{b} \: + \: c)\cdot(\overline{a} \: + \: b \: + \: \overline{c})}$$

what is a karnaugh map (k-map)?

k-map is a graphical tool used for simplifying boolean expressions represented in their standard form to obtain their minimal form.

the k-map is basically a graph or chart that composed of an arrangement of adjacent cells or squares, where each cell represents a particular combination of variables of the function either in sum or product form.

the number of cells in the k-map depends upon number of variables in the boolean function, i.e., k-map has 2ⁿ adjacent cells, where n is the number of variables in the boolean expression. therefore, the number of cells in a 2 variable k-map are 4 (2²), in 3 variable kmap, the number of cells are 8 (2³), in 4 variable k-map, the number of cells are 16 (2⁴), and so on.

however, we can use the k map for any number of variables. but, for simplifying boolean functions in variables more than 5, it becomes tedious.

now, let us discuss the procedure of simplifying a boolean expression using k-map.

steps to simplify a boolean expression using k map

the following steps are involving in simplification of a given boolean expression by using k-map −

step 1 − select a k-map as per the number of variables in the given boolean function.

step 2 − identify the minterms (in sop form) or maxterms (in pos form).

step 3 − for sop (sum of products) form, put 1s in cells of the k-map with respect to the minterms of given function. read the k-map as follows −

read the k-map for 1s which are not adjacent to any other 1. these 1s are the isolated minterms, thus they are to be read as they are, because they cannot be combine in groups.
read the k-map for 1s which are adjacent only one other 1. combine such minterms in 2-squares.
read the k-map for quads (4-squares), octets (8-squares), and so on of adjacent 1s even if they have some 1s which are already combined in other groups. the only thing to remember that they must geometrically form a rectangle or a square.
read the k-map for any 1s that have not been grouped yet and group them into bigger squares or rectangles if possible.
finally, obtain product terms of all the groups, and then sum up them to form the minimal sop expression.

for pos (product of sums) form, put 0s in cells of the k-map with respect to the maxterms of given function. read the k-map as follows −

read the k-map for 0s which are not adjacent to any other 0. these 0s are the isolated maxterms, thus they are to be read as they are, because they cannot be combine in groups.
read the k-map for 0s which are adjacent only one other 0. combine such maxterms in 2-squares.
read the k-map for quads (4-squares), octets (8-squares), and so on of adjacent 0s even if they have some 0s which are already combined in other groups. the only thing to remember that they must geometrically form a rectangle or a square.
read the k-map for any 0s that have not been combined yet and combine them into bigger squares or rectangles if possible.
finally, obtain sum terms of all the groups, and then product them to form the minimal pos expression.

let us understand this procedure of simplifying boolean expression using k-map with the help of some solved examples.

example 1

simplify the following 3-variable boolean function in sop form using k-map.

$$\mathrm{f(p, \: q, \:r) \: = \: \sum m ( 0, \: 1, \: 3, \: 5, \: 7)}$$

solution

the k-map representation of the given boolean function is shown in figure-1.

the simplification of this k-map is done as per the following steps −

there are no isolated 1s.
the minterm m₁ forms a 4-square with minterms m₃, m₅, and m₇. make it and read it as r.
the minterm m₀ forms a 2-square with the minterm m₁. make it and read it as $\mathrm{\bar{p} \: \bar{q}}$
write all the product terms in sop form.

thus, the simplified sop expression is,

$$\mathrm{f \: = \: r \: + \: \bar{p}\bar{q}}$$

example 2

simplify the following 3-variable boolean function in pos form using k-map.

$$\mathrm{f(a, \: b, \: c) \: = \: \pi \: m(1, \: 2, \: 4, \: 6)}$$

solution

the pos k-map representation of the given boolean function is shown in figure-2.

the simplification of this pos k-map is done as per the following steps −

the maxterm m₁ has no adjacency. thus, keep it as it is and read it as $\mathrm{(a \: + \: b \: + \: \bar{c})}$.
the maxterm m₂ has only one adjacency m₆. hence, expand the maxterm m₂ into a 2-square with the maxterm m₆ and read the 2-square as $\mathrm{(\bar{b} \: + \: c)}$.
the maxterm m₄ also has only one adjacency m₆. hence, expand the maxterm m₄ into a 2-square with the maxterm m₆ and read the 2-square as $\mathrm{(\bar{a} \: + \: c)}$.
write all the sum terms in pos form.

therefore, the simplified pos expression is,

$$\mathrm{f \: = \: (a \: + \: b \: + \: \bar{c}) \: (\bar{b} \: + \: c) \: (\bar{a} \: + \: c)}$$

example 3

simplify the following 4-variable boolean function in sop form to obtain the minimal sop expression.

$$\mathrm{f(a, \: b, \: c, \:d) \: = \: \sum \: m( 0,\: 1, \:3, \: 5, \: 7, \: 6, \: 10, \: 13, \: 14, \: 15)}$$

solution

sop k-map representation of the given boolean function is shown in figure-3.

the simplification of this sop k-map is done as per the following steps −

there are no isolated 1s.
the minterm m₁ has three adjacencies m₃, m₅, and m₇. so expand m₁ into a 4-square with minterms m₃, m₅, and m₇, and read the 4-square as $\mathrm{\bar{a}d}$.
the minterm m5 has three adjacencies m₇, m₁₃, and m₁₅. expand m₅ into a 4-square with minterms m₇, m₁₃, and m₁₅, and read the 4-square as bd.
the minterm m6 also has three adjacencies m₇, m₁₄, and m₁₅. expand m6 into a 4- square with minterms m₇, m₁₄, and m₁₅, and read the 4-square as bc.
the minterm m₁₀ has only one adjacency m₁₄. expand m₁₀ into a 2-square with minterm m₁₄ and read the 2-square as $\mathrm{ac\bar{d}}$.
the minterm m₀ also has only one adjacency m₁. expand m₀ into a 2-square with minterm m₁ and read the 2-square as $\mathrm{\bar{a}\bar{b}\bar{c}}$.
write all the product terms in sop form.

hence, the simplified sop expression is,

$$\mathrm{f \: = \: \bar{a}d \: + \: bd \: + \: bc \: + \: ac\bar{d} \: + \: \bar{a}\bar{b}\bar{c}}$$

conclusion

in this way, we can simplify a given boolean expression using k-map to obtain the minimal expression. try solving the following tutorial problems for better understanding.

q. 1 − simplify the following 3-variable boolean function in sop form to obtain its minimal expression.

$$\mathrm{f(a, \: b, \: c) \: = \: \sum \: m(1, \: 2, \: 4, \: 5, \: 7)}$$

q. 2 − simplify the following 4-variable boolean function in sop form to obtain the minimal boolean expression.

$$\mathrm{f(a, \: b, \: c, \: d) \: = \: \sum \: m(0, \: 1, \: 2, \: 4, \: 5, \: 7, \: 8, \: 9, \: 10, \: 12, \: 14, \: 15)}$$

a combinational circuit, also called a combinational logic circuit, is a digital electronic circuit whose output is determined by present inputs only.

the output of a combinational logic circuit does not depend on the history of the circuit operation. in other words, a combinational circuit is a digital logic circuit whose output depends only on the present input values and does not depend on any feedback or previous input or output values.

in this chapter, we will explain the fundamentals of combinational circuits, and its block diagram, types, and applications. so, lets start with the basic definition of combinational circuits.

what is a combinational circuit?

a combinational circuit is a type of digital logic circuit whose output depends on the present input values only and does not depend on past input and output values. therefore, a combinational circuit is considered to not have a memory element in its circuit that stores previous inputs and outputs. instead, it consists of a certain number of input lines to apply current input values and a certain number of output lines.

the most important characteristic of a combinational circuit is that it does not have any feedback path between input and output. therefore, the combinational circuits can be categorized as open-loop systems.

block diagram of combinational circuit

the following figure depicts the block diagram of a combinational logic circuit.

here, we can see that there are only three key elements in the circuit diagram of a combinational circuit, they are −

input lines − the input lines are used to enter the input values into the combinational circuit.
processing unit − it is the main element that processes the input values depending on the type of the circuit. for example, a full adder adds three binary bits.
output lines − the output lines are used to take results generated by the circuit.

characteristics of combinational circuits

the following are the main characteristics of combinational circuits −

the output of a combinational circuit, at any instant of time, depends only on the present input values at that instant of time.
combinational circuits do not use any kind of memory element in their circuits. thus, the previous state of input and output values do not have any effect on the present operation of the circuit.
the output of a combinational circuit can be entirely predicted using its logical operation and input values.
combinational circuits produce an instantaneous output in response to any change in its input values.

types of combinational circuits

in digital electronics, the combinational circuits are important components of digital systems. depending on the functions performed, there are various types of combinational circuits. some common types of combinational circuits and their functions are explained below −

binary adders
binary subtractors
multiplexers (mux)
demultiplexers (demux)
encoders
decoders
comparators

in the following sections of this chapter, we will discuss briefly about each of these combinational circuits along with their functions.

binary adders

a binary adder is a combinational circuit that performs the addition of binary digits or bits. depending on the design and configuration, there are two types of binary adders namely, half adder and full adder.

half adder

the half adder is a combinational logic circuit with two inputs and two outputs. the half adder circuit is designed to add two single-bit binary numbers a and b. it is the basic building block for the addition of two single-bit numbers. this circuit has two outputs namely, sum and carry.

full adder

the full adder is designed to overcome the drawback of a half adder which is the ability to add only two bits. therefore, the full adder is a three-input and two-output combinational circuit. where, the inputs are two one-bit numbers a and b, and a carry c from the previous addition. the outputs are sum and carry output.

binary subtractors

a binary subtractor is a combinational logic circuit used to subtract one binary number from another. similar to binary adder, there are two types of binary subtractors namely, half-subtractor and full-subtractor.

half subtractor

a half subtractor is a combination circuit with two inputs (a and b) and two outputs (difference and borrow). it produces the difference between the two binary bits at the input and also produces an output (borrow) to indicate if a 1 has been borrowed. in binary subtraction (a-b), a is called a minuend bit and b is called a subtrahend bit.

full subtractor

the full subtractor is also a combinational circuit with three inputs a, b, and b_in, and two outputs d and b_out.

here, a is the minuend bit, b is the subtrahend bit, b_in is the previous borrow bit produced by the previous stage, d is the difference output and b_out is the borrow output.

multiplexers (mux)

a multiplexer is a special type of combinational logic circuit. it consists of n-data input lines, one output, and m-select lines. for a multiplexer, n = 2^m.

a multiplexer is a digital circuit that selects one of the n data inputs and routes it to the output line. the selection of one of the n data inputs is done by the select lines. depending on the digital code applied at the select lines, one out of "n" data inputs is selected and transmitted to the output line.

in some multiplexers, there is also an enable input e which is useful in cascading of multiple multiplexers.

depending on the number of input lines, there can be several types of multiplexers. some common types of multiplexers include 2:1 multiplexer, 4:1 multiplexer, 16:1 multiplexer, and 32:1 multiplexer.

demultiplexers (demux)

a demultiplexer performs a distribution operation i.e., it receives one data input and distributes it over several output lines.

a demultiplexer has only one input line, "n" output lines, and "m" select lines. at a time, only one output line is selected by the digital code applied to the select lines and the data input is transmitted to the selected output line.

demultiplexers can be classified into various types depending on the number of output lines. some commonly used types of demultiplexers include: 1:2 demultiplexer, 1:4 demultiplexer, 1:16 demultiplexer, and 1:32 demultiplexer.

encoders

an encoder is a combinational circuit that is designed to convert a piece of information into a binary code. an encoder has n number of input lines and m number of output lines, where n = 2^m.

an encoder generates an m-bit binary code corresponding to the digital input applied to it. in other words, an encoder accepts an n-input digital word and converts it into an m-bit another digital word.

examples of encoder include 4-to-2 encoder, octal-to-binary encoder, hexadecimal-to-binary encoder, priority encoder, etc.

decoders

a decoder is a combinational circuit that converts a binary code into a normal word like a decimal digit. a decoder typically consists of n input lines and m output lines, where the m = 2ⁿ.

decoders are widely used in display drivers, data distribution systems, etc.

some of the commonly used types of decoders are 2 to 4 decoder, 3 to 8 decoder, 4 to 16 decoder, bcd to seven segment decoder, etc.

comparators

a comparator is a combinational logic circuit developed to compare two binary numbers. comparators are mainly used in arithmetic and control circuits to perform comparison or logical operations.

a comparator, as its name suggests, compares the input values and checks whether they are equal or one input is greater/less than the other input.

limitations of combinational circuits

combinational circuits have several advantages such as fast operational speed, simpler circuit, predictable operation, etc. however, they do have several limitations too, some of which are listed below −

combinational circuits do not have any memory element. they are incapable to store history of circuit operation.
combinational circuits cannot be used to implement certain highly complex logic functions.
combinational circuits do not have any feedback mechanism. that makes the combinational circuits to have limited functionality.
at large scale, combinational circuits have several design complexities that can result in poor performance and inefficient resource utilization.

applications of combinational circuits

combinational circuits are the fundamental building blocks in various digital devices and systems. they are widely used in several digital devices in which combinational circuits are used −

microprocessors and microcontrollers
digital computers
calculators
digital communication systems
keyboards
smartphones and digital watches, etc

conclusion

a combinational logic circuit is a key component in various digital devices and systems. it can be defined as an interconnected system of digital components whose output depends only on the present states of inputs and it does not depend on past input and output values.

in this chapter, we explained the characteristics, limitations, and applications of combinational circuits.

in this chapter, let us discuss about the basic arithmetic circuits like binary adder and binary subtractor. these circuits can be operated with binary values 0 and 1.

binary adder

the most basic arithmetic operation is addition. the circuit, which performs the addition of two binary numbers is known as binary adder. first, let us implement an adder, which performs the addition of two bits.

half adder

half adder is a combinational circuit, which performs the addition of two binary numbers a and b are of single bit. it produces two outputs sum, s & carry, c.

the truth table of half adder is shown below.

inputs		outputs
a	b	c	s
0	0	0	0
0	1	0	1
1	0	0	1
1	1	1	0

when we do the addition of two bits, the resultant sum can have the values ranging from 0 to 2 in decimal. we can represent the decimal digits 0 and 1 with single bit in binary. but, we cant represent decimal digit 2 with single bit in binary. so, we require two bits for representing it in binary.

let, sum, s is the least significant bit and carry, c is the most significant bit of the resultant sum. for first three combinations of inputs, carry, c is zero and the value of s will be either zero or one based on the number of ones present at the inputs. but, for last combination of inputs, carry, c is one and sum, s is zero, since the resultant sum is two.

from truth table, we can directly write the boolean functions for each output as

$$\mathrm{s \: = \: a \: \oplus \: b}$$

$$\mathrm{c \: = \: ab}$$

we can implement the above functions with 2-input ex-or gate & 2-input and gate. the circuit diagram of half adder is shown in the following figure.

in the above circuit, a two input ex-or gate & two input and gate produces sum, s & carry, c respectively. therefore, half-adder performs the addition of two bits.

full adder

full adder is a combinational circuit, which performs the addition of three bits a, b and c_in. where, a & b are the two parallel significant bits and c_in is the carry bit, which is generated from previous stage. this full adder also produces two outputs sum, s & carry, c_out, which are similar to half adder.

the truth table of full adder is shown below.

inputs			outputs
a	b	c_in	c_out	s
0	0	0	0	0
0	0	1	0	1
0	1	0	0	1
0	1	1	1	0
1	0	0	0	1
1	0	1	1	0
1	1	0	1	0
1	1	1	1	1

when we do the addition of three bits, the resultant sum can have the values ranging from 0 to 3 in decimal. we can represent the decimal digits 0 and 1 with single bit in binary. but, we cant represent the decimal digits 2 and 3 with single bit in binary. so, we require two bits for representing those two decimal digits in binary.

let, sum, s is the least significant bit and carry, c_out is the most significant bit of resultant sum. it is easy to fill the values of outputs for all combinations of inputs in the truth table. just count the number of ones present at the inputs and write the equivalent binary number at outputs. if c_in is equal to zero, then full adder truth table is same as that of half adder truth table.

we will get the following boolean functions for each output after simplification.

$$\mathrm{s \: = \: a \: \oplus \: b \: \oplus \: c_{in}}$$

$$\mathrm{c_{out} \: = \: ab \: + \: \left ( a \: \oplus \: b \right ) \: c_{in}}$$

the sum, s is equal to one, when odd number of ones present at the inputs. we know that ex-or gate produces an output, which is an odd function. so, we can use either two 2input ex-or gates or one 3-input ex-or gate in order to produce sum, s. we can implement carry, c_out using two 2-input and gates & one or gate. the circuit diagram of full adder is shown in the following figure.

this adder is called as full adder because for implementing one full adder, we require two half adders and one or gate. if c_in is zero, then full adder becomes half adder. we can verify it easily from the above circuit diagram or from the boolean functions of outputs of full adder.

4-bit binary adder

the 4-bit binary adder performs the addition of two 4-bit numbers. let the 4-bit binary numbers, $\mathrm{a \: = \: a_{3}a_{2}a_{1}a_{0}}$ and $\mathrm{b \: = \: b_{3}b_{2}b_{1}b_{0}}$. we can implement 4-bit binary adder in one of the two following ways.

use one half adder for doing the addition of two least significant bits and three full adders for doing the addition of three higher significant bits.
use four full adders for uniformity. since, initial carry c_in is zero, the full adder which is used for adding the least significant bits becomes half adder.

for the time being, we considered second approach. the block diagram of 4-bit binary adder is shown in the following figure.

here, the 4 full adders are cascaded. each full adder is getting the respective bits of two parallel inputs a & b. the carry output of one full adder will be the carry input of subsequent higher order full adder. this 4-bit binary adder produces the resultant sum having at most 5 bits. so, carry out of last stage full adder will be the msb.

in this way, we can implement any higher order binary adder just by cascading the required number of full adders. this binary adder is also called as ripple carry (binary) adder because the carry propagates (ripples) from one stage to the next stage.

binary subtractor

the circuit, which performs the subtraction of two binary numbers is known as binary subtractor. we can implement binary subtractor in following two methods.

cascade full subtractors
2s complement method

in first method, we will get an n-bit binary subtractor by cascading 'n' full subtractors. so, first you can implement half subtractor and full subtractor, similar to half adder & full adder. then, you can implement an n-bit binary subtractor, by cascading n full subtractors. so, we will be having two separate circuits for binary addition and subtraction of two binary numbers.

in second method, we can use same binary adder for subtracting two binary numbers just by doing some modifications in the second input. so, internally binary addition operation takes place but, the output is resultant subtraction.

we know that the subtraction of two binary numbers a & b can be written as,

$$\mathrm{a-b \: = \: a \: + \: \left ( {2}'s \: compliment \: of \: b \right )}$$

$$\mathrm{\rightarrow \: a \: - \: b \: = \: a \: + \: \left ( {1}'s \: compliment \: of \: b \right ) \: + \: 1}$$

4-bit binary subtractor

the 4-bit binary subtractor produces the subtraction of two 4-bit numbers. let the 4bit binary numbers, $\mathrm{a \: = \: a_{3}a_{2}a_{1}a_{0}}$ and $\mathrm{b \: = \: b_{3}b_{2}b_{1}b_{0}}$. internally, the operation of 4-bit binary subtractor is similar to that of 4-bit binary adder. if the normal bits of binary number a, complemented bits of binary number b and initial carry (borrow), c_in as one are applied to 4-bit binary adder, then it becomes 4-bit binary subtractor. the block diagram of 4-bit binary subtractor is shown in the following figure.

this 4-bit binary subtractor produces an output, which is having at most 5 bits. if binary number a is greater than binary number b, then msb of the output is zero and the remaining bits hold the magnitude of a-b. if binary number a is less than binary number b, then msb of the output is one. so, take the 2s complement of output in order to get the magnitude of a-b.

in this way, we can implement any higher order binary subtractor just by cascading the required number of full adders with necessary modifications.

binary adder / subtractor

the circuit, which can be used to perform either addition or subtraction of two binary numbers at any time is known as binary adder / subtractor. both, binary adder and binary subtractor contain a set of full adders, which are cascaded. the input bits of binary number a are directly applied in both binary adder and binary subtractor.

there are two differences in the inputs of full adders that are present in binary adder and binary subtractor.

the input bits of binary number b are directly applied to full adders in binary adder, whereas the complemented bits of binary number b are applied to full adders in binary subtractor.
the initial carry, c₀ = 0 is applied in 4-bit binary adder, whereas the initial carry (borrow), c₀ = 1 is applied in 4-bit binary subtractor.

we know that a 2-input ex-or gate produces an output, which is same as that of first input when other input is zero. similarly, it produces an output, which is complement of first input when other input is one.

therefore, we can apply the input bits of binary number b, to 2-input ex-or gates. the other input to all these ex-or gates is c₀. so, based on the value of c₀, the ex-or gates produce either the normal or complemented bits of binary number b.

4-bit binary adder / subtractor

the 4-bit binary adder / subtractor produces either the addition or the subtraction of two 4-bit numbers based on the value of initial carry or borrow, ₀. let the 4-bit binary numbers, $\mathrm{a \: = \: a_{3}a_{2}a_{1}a_{0}}$ and $\mathrm{b \: = \: b_{3}b_{2}b_{1}b_{0}}$. the operation of 4-bit binary adder / subtractor is similar to that of 4-bit binary adder and 4-bit binary subtractor.

apply the normal bits of binary numbers a and b & initial carry or borrow, c₀ from externally to a 4-bit binary adder. the block diagram of 4-bit binary adder / subtractor is shown in the following figure.

if initial carry, ₀ is zero, then each full adder gets the normal bits of binary numbers a & b. so, the 4-bit binary adder / subtractor produces an output, which is the addition of two binary numbers a & b.

if initial borrow, ₀ is one, then each full adder gets the normal bits of binary number a & complemented bits of binary number b. so, the 4-bit binary adder / subtractor produces an output, which is the subtraction of two binary numbers a & b.

therefore, with the help of additional ex-or gates, the same circuit can be used for both addition and subtraction of two binary numbers.

a digital logic circuit that accepts several data inputs and allows only one of them at a time to flow through the output is called a multiplexer or mux. this article is meant for explaining multiplexer in digital electronics, its block diagram, function, and different types. so, let us start with the basic introduction of multiplexer

what is a multiplexer?

as already mentioned, a multiplexer, also referred to as mux, is a combination logic circuit that is designed to accept multiple input signals and transfer only one of them through the output line. in simple words, a multiplexer is a digital logic device that selects one-out-of-n (n = 2ⁿ) input data sources and transmits the selected data to a single output line.

the multiplexer is also called data selector as it selects one from several. the block diagram of a typical 2ⁿ:1 multiplexer is shown in figure 1.

in the case of multiplexer, the selection of desired data input to flow through the output line is controlled with the help of select lines. in the block diagram of mux in figure 1, i₀, i₁,... i_n-1, i.e., (2ⁿ) are the input lines, and "n" be the select lines. these select lines will determine which input is to be routed to the output.

hence, the multiplexer works as a multi-position switch whose operation is controlled by digital signals. these digital control signals are applied to the select lines to determine which data input will be switched to the output line.

function of multiplexer

multiplexer is a digital logic device which is used to perform multiplexing of data. where, multiplexing simply means sharing of data. technically, when a particular data is selected from multiple input data sources and transmitted the selected data to a single output channel, it is called multiplexing.

there are two types of multiplexing namely, frequency multiplexing and time multiplexing.

when multiple devices are connected to a single transmission line in a system. at any point of time, only one device is using the line to transmit data, then this is called time multiplexing. on the other hand, when multiple devices share a common line to transmit data but at different frequencies, it is called frequency multiplexing.

types of multiplexers

based on input data lines and select lines, the multiplexer can be of several types. but, in this article, we will discuss only the following three types of multiplexers −

2×1 multiplexer
4×1 multiplexer

let us discuss each of these three multiplexers individually.

2×1 multiplexer

the block diagram of a 2×1 multiplexer is shown in figure 2. the 2×1 multiplexer is basic two input multiplexer which has two data input lines designated as i₀ and i₁, one data select line denoted by s and one output line denoted by y. the 2×1 mux is used to connect two 1-bit data sources to a common designation.

in the 2×1 multiplexer, the logic level of the digital signal applied to the select line s determines which data input will pass through the output line. the operation of the 2×1 multiplexer can be understood from the following truth table.

select line (s)	output (y)
0	i₀
1	i₁

4×1 multiplexer

4×1 multiplexer has four data inputs i₃, i₂, i₁ & i₀, two selection lines s₁ & s₀ and one output y. the block diagram of 4×1 multiplexer is shown in the following figure.

one of these 4 inputs will be connected to the output based on the combination of inputs present at these two selection lines. truth table of 4×1 multiplexer is shown below.

selection lines		output
s₁	s₀	y
0	0	i₀
0	1	i₁
1	0	i₂
1	1	i₃

from truth table, we can directly write the boolean function for output, y as

$$\mathrm{y\:=\:{s_{1}}'{s_{0}}'i_{0}\:+\:{s_{1}}'s_{0}i_{1}\:+\:s_{1}{s_{0}}'i_{2}\:+\:s_{1}s_{0}i_{3}}$$

we can implement this boolean function using inverters, and gates & or gate. the circuit diagram of 4×1 multiplexer is shown in the following figure.

we can easily understand the operation of the above circuit. similarly, you can implement 8×1 multiplexer and 16×1 multiplexer by following the same procedure.

implementation of higher-order multiplexers

now, let us implement the following two higher-order multiplexers using lower-order multiplexers.

8×1 multiplexer
16×1 multiplexer

8×1 multiplexer

in this section, let us implement 8×1 multiplexer using 4×1 multiplexers and 2×1 multiplexer. we know that 4×1 multiplexer has 4 data inputs, 2 selection lines and one output. whereas, 8×1 multiplexer has 8 data inputs, 3 selection lines and one output.

so, we require two 4×1 multiplexers in first stage in order to get the 8 data inputs. since, each 4×1 multiplexer produces one output, we require a 2×1 multiplexer in second stage by considering the outputs of first stage as inputs and to produce the final output.

let the 8×1 multiplexer has eight data inputs i₇ to i₀, three selection lines s₂, s₁ & s0 and one output y. the truth table of 8×1 multiplexer is shown below.

selection inputs			output
s₂	s₁	s₀	y
0	0	0	i₀
0	0	1	i₁
0	1	0	i₂
0	1	1	i₃
1	0	0	i₄
1	0	1	i₅
1	1	0	i₆
1	1	1	i₇

we can implement 8×1 multiplexer using lower order multiplexers easily by considering the above truth table. the block diagram of 8×1 multiplexer is shown in the following figure.

the same selection lines, s₁ & s₀ are applied to both 4×1 multiplexers. the data inputs of upper 4×1 multiplexer are i₇ to i₄ and the data inputs of lower 4×1 multiplexer are i₃ to i₀. therefore, each 4×1 multiplexer produces an output based on the values of selection lines, s₁ & s₀.

the outputs of first stage 4×1 multiplexers are applied as inputs of 2×1 multiplexer that is present in second stage. the other selection line, s₂ is applied to 2×1 multiplexer.

if s₂ is zero, then the output of 2×1 multiplexer will be one of the 4 inputs i₃ to i₀ based on the values of selection lines s₁ & s₀.
if s₂ is one, then the output of 2×1 multiplexer will be one of the 4 inputs i₇ to i₄ based on the values of selection lines s₁ & s₀.

therefore, the overall combination of two 4×1 multiplexers and one 2×1 multiplexer performs as one 8×1 multiplexer.

16×1 multiplexer

in this section, let us implement 16×1 multiplexer using 8×1 multiplexers and 2×1 multiplexer. we know that 8×1 multiplexer has 8 data inputs, 3 selection lines and one output. whereas, 16×1 multiplexer has 16 data inputs, 4 selection lines and one output.

so, we require two 8×1 multiplexers in first stage in order to get the 16 data inputs. since, each 8×1 multiplexer produces one output, we require a 2×1 multiplexer in second stage by considering the outputs of first stage as inputs and to produce the final output.

let the 16×1 multiplexer has sixteen data inputs i₁₅ to i₀, four selection lines s₃ to s₀ and one output y. the truth table of 16×1 multiplexer is shown below.

selection inputs				output
s₃	s₂	s₁	s₀	y
0	0	0	0	i₀
0	0	0	1	i₁
0	0	1	0	i₂
0	0	1	1	i₃
0	1	0	0	i₄
0	1	0	1	i₅
0	1	1	0	i₆
0	1	1	1	i₇
1	0	0	0	i₈
1	0	0	1	i₉
1	0	1	0	i₁₀
1	0	1	1	i₁₁
1	1	0	0	i₁₂
1	1	0	1	i₁₃
1	1	1	0	i₁₄
1	1	1	1	i₁₅

we can implement 16×1 multiplexer using lower order multiplexers easily by considering the above truth table. the block diagram of 16×1 multiplexer is shown in the following figure.

the same selection lines, s₂, s₁ & s₀ are applied to both 8×1 multiplexers. the data inputs of upper 8×1 multiplexer are i₁₅ to i₈ and the data inputs of lower 8×1 multiplexer are i₇ to i₀. therefore, each 8×1 multiplexer produces an output based on the values of selection lines, s₂, s₁ & s₀.

the outputs of first stage 8×1 multiplexers are applied as inputs of 2×1 multiplexer that is present in second stage. the other selection line, s₃ is applied to 2×1 multiplexer.

if s₃ is zero, then the output of 2×1 multiplexer will be one of the 8 inputs is₇ to i₀ based on the values of selection lines s₂, s₁ & s₀.

if s₃ is one, then the output of 2×1 multiplexer will be one of the 8 inputs i₁₅ to i₈ based on the values of selection lines s₂, s₁ & s₀.

therefore, the overall combination of two 8×1 multiplexers and one 2×1 multiplexer performs as one 16×1 multiplexer.

applications of multiplexers

in digital electronics, multiplexers have numerous applications in almost all types of digital systems. some important applications of multiplexers are as follows −

data routing and data selection
parallel to series conversion
logic function implementation
generation of waveform, etc.

conclusion

in this tutorial, we discussed in detail the different types of multiplexers used in digital electronics along with their functions and applications.

in the field of digital electronics, it is very important to ensure the data integrity. for this purpose, we have two digital circuits namely, parity generator and parity checker. both these circuits help us to detect and correct any kind of error in transmitted data.

read this chapter to learn the basics of parity generator and parity checker, along with their types and applications.

what is a parity bit?

in digital signal processing, an additional bit either 0 or 1 is added to the original binary or digital code to detect and correct any kind of errors in the data that can occur during transmission. this additional bit is called a parity bit.

the addition of a parity bit to the original digital code makes the total number of 1s in the code either even or odd. thus, on the basis of number 1s in the data, the parity can be classified into two types namely, even parity and odd parity.

if we add a 0 or a 1 to the original binary code and this makes the total number of 1s in the code an even number, then it is called an even parity.

on the other hand, if we add a parity bit i.e., 0 or 1 to the original binary code and this makes the total number of 1s in the code an odd number, then it is called an odd parity.

the parity bit is one of the simplest forms of error-detection technique used in digital electronics.

how does the parity bit work?

let us now consider an example to understand how the parity bit works.

suppose we have a decimal number say 5 and its bcd code is 0101. this code has total number of 1s are even, as it has two 1s.

in the case of even parity, we add a parity bit 0 to the original code to make the number of 1s an even number in the code.

therefore, after adding even parity, we get 01010. here, a 0 (parity bit) is added to the end of the original code.

in case, when we need to perform odd parity, then we add a 1 to end of the original code, we get 01011. now, the total number of 1s in the code, including parity bit, is odd i.e., three 1s. this ensures that it is odd parity scheme.

the following table shows the odd and even parity bits for decimal digits from 0 to 9 −

decimal digit	bcd	even parity	odd parity
0	0 0 0 0	0	1
1	0 0 0 1	1	0
2	0 0 1 0	1	0
3	0 0 1 1	0	1
4	0 1 0 0	1	0
5	0 1 0 1	0	1
6	0 1 1 0	0	1
7	0 1 1 1	1	0
8	1 0 0 0	1	0
9	1 0 0 1	0	1

when a digital signal is received at the receiver end, a parity checker circuit generates an error signal if the total number of 1s is an odd number in an even parity scheme or an even number in an odd parity scheme.

the major limitation of parity bit error detection technique is that it can check only a single-bit error, but cannot check a multi bit error.

what is a parity generator?

a combinational logic circuit that can generate the parity bit according to the original digital code is known as a parity bit generator or parity generator.

the parity generator is used at the transmitter end and generate and add a parity bit the original code before transmission.

first, a parity generator reads the input data and calculates the parity bit accordingly. once the parity bit is generated, it is added to the original data code. this gives an output code which is the original code with a newly generated parity bit.

types of parity generators

depending on the parity system used, there are two main types of parity generators −

even parity generator
odd parity generator

let us discuss about even and odd parity generators in detail.

even parity generator

an even parity generator is a type of parity generator in which the parity bit, either a 0 or a 1 is added to the original data so that the final digital code contains an even number of 1s, including the parity bit.

therefore, we can state that total number of 1s in the output of an even parity generator including the parity bit is even.

in the case of an even parity generator −

if a digital code contains an odd number of 1s, then the even parity generator will generate a 1 as parity bit to maintain the even parity.
if a digital code already contains an even number of 1s, then the even parity generator will generate a 0 as the parity bit to maintain the even parity.

for example, consider a digital code 0110. this code already contains the even number of 1s. hence, if it is input to an even parity generator, the output of the parity generator will be 01100. where, the lsb 0 is a parity bit added by the even parity generator.

similarly, consider another digital code 0111. in this case, the total number of 1s in the code is three (odd). if we input this code to an even parity generator, the generators output will be 01111, containing even number of 1s. where, the lsb 1 is the parity bit.

let us now design a 4-bit even parity generator. the following is the truth table of the 4-bit even parity generator −

4-bit code				even parity
a	b	c	d	p
0	0	0	0	0
0	0	0	1	1
0	0	1	0	1
0	0	1	1	0
0	1	0	0	1
0	1	0	1	0
0	1	1	0	0
0	1	1	1	1
1	0	0	0	1
1	0	0	1	0
1	0	1	0	0
1	0	1	1	1
1	1	0	0	0
1	1	0	1	1
1	1	1	0	1
1	1	1	1	0

the boolean expression of the 4-bit even parity generator can be obtained by simplifying its truth table, which is given below.

$$\mathrm{p \: = \: a \: \oplus \: b \: \oplus \: c \: \oplus \: d}$$

the logic circuit diagram of a 4-bit even parity generator is shown in the following figure.

in this circuit, three xor gates are connected together to add four data bits of the input code. the sum bit produced at the output will be the parity bit.

this is all about the even parity generator and its functioning.

odd parity generator

a type of parity generator that adds a parity bit to a binary code so that the total number of 1s in the output code is an odd number, it is called an odd parity generator.

the output of an odd parity generator is a digital code that contains an odd number of 1s, including the parity bit.

in the case of an odd parity generator,

if the original data contains an even number of 1s, then the odd parity generator adds a 1 as parity bit to the original code to maintain the odd parity.
if the original data already contains an odd number of 1s, then the odd parity generator adds a 0 as parity bit to the original code to maintain the odd parity.

let us understand the function of the odd parity generator with the help of examples.

consider a 4-bit digital code that is 0110. this code has even number of 1s (two). therefore, if we input this code to an odd parity generator, the generator will add a 1 and produces a code 01101 as output. this resulting code has odd number of 1s, including the parity bit, and ensuring the odd parity system.

similarly, consider another 4-bit code that is 0111. this code already contains odd number of 1s i.e., three 1s. therefore, the odd parity generator will add a 0 as parity bit to it and gives an output code as 01110 to ensure the odd parity system.

the following is the truth table of a 4-bit odd parity generator −

4-bit code				odd parity
a	b	c	d	p
0	0	0	0	1
0	0	0	1	0
0	0	1	0	0
0	0	1	1	1
0	1	0	0	0
0	1	0	1	1
0	1	1	0	1
0	1	1	1	0
1	0	0	0	0
1	0	0	1	1
1	0	1	0	1
1	0	1	1	0
1	1	0	0	1
1	1	0	1	0
1	1	1	0	0
1	1	1	1	1

the boolean expression of the 4-bit odd parity generator is,

$$\mathrm{p \: = \: \overline{a \: \oplus \: b \: \oplus \: c \: \oplus \: d}}$$

the following figure depicts the logic circuit diagram of the 4-bit odd parity generator.

in this circuit, three xor gates are connected together to add the four bits of the input data and the sum bit is then complemented to obtain the odd parity bit.

this is all about the even parity generator and odd parity generator. both of these types of parity generators are used in digital systems to implement different types of parity systems depending on the needs of the applications.

parity generators are extensively used in digital communication and storage systems to check errors that can occur during transmission of data.

what is a parity checker?

a combinational circuit that checks and verifies the correctness of the transmitted data by analyzing the parity bit is called a parity checker. the main function of a parity checker is to detect errors that can occur during data transmission.

parity checkers are used at the receiver end of the communication channel. it receives the transmitted data from the communication channel. this data includes the original message code and the parity bit.

after that, the parity checker counts the number of 1s in the data code and compares this number with the expected code to determine whether there is any error or not. if there is any error in the received data, the parity checker takes an appropriate action like request to retransmit the data.

the parity checker is an essential component in the digital communication systems to ensure the correctness and integrity of data. it also provides a simple and effective method for error detection.

types of parity checkers

depending on the parity system used, there are two main types of parity checkers −

even parity checker
odd parity checker

let us discuss each type of parity checker in detail.

even parity checker

the type of parity checker that verifies whether the received data is correct as per the even parity system is called an even parity checker.

the even parity checker counts and verifies that the received data contains an even number of 1s, including the parity bit.

thus, in the case of an even parity checker,

if the number of 1s in the received data is even, then it is considered that the data is error free.
if the number of 1s in the received data is odd, then the parity checker shows that the data contains some error.

how does an even parity checker work?

let us understand the even parity checking with the help of an example.

consider a 4-bit digital code 00110 (having 0 as parity bit at lsb position), this code is received by the even parity checker. the parity checker will count the number of 1s in the code which is even (two). thus, the parity checker shows that it is an error free code, where lsb 0 is the parity bit.

similarly, consider another 4-bit message code 01011 with a parity bit at the lsb place. this code contains odd number of 1s (three 1s). hence, the even parity checker will show that the code has some error.

let us now implement a 4-bit even parity checker whose truth table is shown below −

4-bit code with parity					even parity check
a	b	c	d	p	c_p
0	0	0	0	0	0
0	0	0	0	1	1
0	0	0	1	0	1
0	0	0	1	1	0
0	0	1	0	0	1
0	0	1	0	1	0
0	0	1	1	0	0
0	0	1	1	1	1
0	1	0	0	0	1
0	1	0	0	1	0
0	1	0	1	0	0
0	1	0	1	1	1
0	1	1	0	0	0
0	1	1	0	1	1
0	1	1	1	0	1
0	1	1	1	1	0
1	0	0	0	0	1
1	0	0	0	1	0
1	0	0	1	0	0
1	0	0	1	1	1
1	0	1	0	0	0
1	0	1	0	1	1
1	0	1	1	0	1
1	0	1	1	1	0
1	1	0	0	0	0
1	1	0	0	1	1
1	1	0	1	0	1
1	1	0	1	1	0
1	1	1	0	0	1
1	1	1	0	1	0
1	1	1	1	0	0
1	1	1	1	1	1

here, the bits abcd represents the original digital code and p is the parity bit.

in this truth table, if c_p = 1, there will be an error in the received code. if c_p = 0, there is no error in the received code.

the boolean expression of the 4-bit even parity checker is,

$$\mathrm{c_{p} \: = \: a \: \oplus \: b \: \oplus \: c \: \oplus \: d \: \oplus \: p}$$

the logic circuit diagram of the 4-bit even parity checker is shown in the following figure.

4-bit even parity generator circuit diagram

odd parity checker

an odd parity checker is a combinational logic circuit that checks and verifies whether the received data is correct as per the odd parity system.

an odd parity checker counts and confirms that the received data contains odd number of 1s including the parity bit.

in the case of an odd parity checker,

if the number of 1s in the received code is odd, there is no error in the code.
if the number of 1s in the received code is even, this represents an error in the code that might be occurred during transmission.

for example, consider a 4-bit data code 01101 (lsb 1 is the parity bit). in this code, the number of 1s are odd (three). thus, the odd parity checker will show that the code is error free.

similarly, consider another 4-bit data code 01100 (lsb 0 is the parity bit). this code contains the even number of 1s i.e., only two 1s are there. in this case, the odd parity checker will show that the code has an error.

let us now implement a 4-bit odd parity checker whose truth table is shown below.

4-bit code with parity					odd parity check
a	b	c	d	p	c_p
0	0	0	0	0	1
0	0	0	0	1	0
0	0	0	1	0	0
0	0	0	1	1	1
0	0	1	0	0	0
0	0	1	0	1	1
0	0	1	1	0	1
0	0	1	1	1	0
0	1	0	0	0	0
0	1	0	0	1	1
0	1	0	1	0	1
0	1	0	1	1	0
0	1	1	0	0	1
0	1	1	0	1	0
0	1	1	1	0	0
0	1	1	1	1	1
1	0	0	0	0	0
1	0	0	0	1	1
1	0	0	1	0	1
1	0	0	1	1	0
1	0	1	0	0	1
1	0	1	0	1	0
1	0	1	1	0	0
1	0	1	1	1	1
1	1	0	0	0	1
1	1	0	0	1	0
1	1	0	1	0	0
1	1	0	1	1	1
1	1	1	0	0	0
1	1	1	0	1	1
1	1	1	1	0	1
1	1	1	1	1	0

in this truth table, the bits abcd represents the original binary code and p is the parity bit.

from this truth table, we can observe that if c_p = 1, the code contains an even number of 1s and hence, there is an error occurred in the code during transmission.

if c_p = 0, the code contains odd number of 1s which represents that the code is error free.

the boolean expression of the 4-bit odd parity checker is given here,

$$\mathrm{c_{p} \: = \: \overline{a \: \oplus \: b \: \oplus \: c \: \oplus \: d \: \oplus \: p}}$$

the logic circuit diagram of this 4-bit odd parity checker is depicted in the following figure.

4-bit odd parity bit generator circuit diagram

ic 74180 9-bit parity generators/checkers

a parity generator/checker ic is a small device which is used to detect errors in data streams transmitted over a communication channel. there are several different parity generator/checker ic available in the market, but one most commonly used is 74180 ic.

the 74180 parity generator/checker ic is a 9-bit parity generator or checker device that is used in high-speed data transmission systems to detect errors.

the pin diagram of the parity generator/checker ic 74180 is shown in the following figure.

it consists of eight input lines labeled from a to h, two cascading input lines labeled as "even" and "odd", and two output lines designated as "even sum" and "odd sum".

depending on the operating mode selected, the ic 74180 can operate as either a parity generator or a parity checker.

let us now consider an example to understand the how does the parity generator/checker ic work?

if the ic 74180 is operated as an even parity checker and there is a parity error in the received data. in this case, the output "even sum" will be low and the output "odd sum" will be high.

if the ic 74180 is operated as an odd parity checker and an error occurs in the data stream. the output "odd sum" will be low and the output "even sum" will be high.

this is all about parity generator or checker ic 74180. let us now discuss the applications of parity generators/checkers.

applications of parity generators and checkers

in digital systems, like digital communication and storage systems, the parity generator and checker are essential components that provide a robust method for error detection and correction in transmitted and retrieved data streams. thus, parity generator/checker helps to ensure data integrity, reliability, and security of digital data.

the following examples illustrate the applications of parity generators and checkers in various digital electronic applications −

in digital communication systems, parity generators and checkers are used to ensure integrity and accuracy of the transmitted and received data. parity generators and checkers help to detect errors in the data that can be caused due to noise and interference during transmission over communication channels.
parity generators and checkers are used in storage systems like ram and rom to detect errors in the data stored and retrieved.
in digital networking, parity generators and checkers are used to improve reliability of data transmission and verify the correctness of the transmitted data.
parity generators and checkers are used in industrial automation and control systems to ensure accurate and reliable operation of industrial systems.
parity generators and checkers are also used in medical equipment used to diagnose and monitor patients health and avoid any kind errors in medical reports and diagnosis data.

conclusion

a parity generator is a combinational logic circuit used to generate and add a parity to the input or transmitted data, while a parity checker is also a combinational circuit used to verify the correctness of received data.

parity generators are used in the transmitter circuit and parity checkers are used in the receiver circuit. both these circuits are collectively used to ensure the reliability, integrity, and accuracy of data in various digital systems.

in digital electronics, a comparator is a combinational logic circuit that is used to compare the magnitudes of two binary numbers. comparators are used in several different electronic circuits like analog to digital converters, voltage level detectors, zero-crossing detectors, etc.

the most basic example of a comparator is an xnor gate which produces a high or logic 1 output only when both its inputs are equal.

in this chapter, we will learn about the basics, types, and applications of comparators in digital electronics. so, lets start with the basic definition of a comparator.

what is a comparator?

a digital combinational circuit used to compare the magnitude of two binary numbers to determine the equality or non-equality is called a comparator.

therefore, the main function of a comparator is to compare the values of input numbers and produce an output indicating whether the numbers are equal or specifies which of the numbers is greater.

let us understand the working of a comparator with the help of an example.

consider two 3-bit binary numbers a₂a₁a₀ and b₂b₁b₀. these two binary numbers are said to be equal if all their corresponding bits coincide. in other words, these two binary numbers are equal if a₂ = b₂, a₁ = b₁, and a₀ = b₀.

the block diagram of a typical comparator is shown in the following figure −

here, a and b are the input bits, and l, e, and g are the output lines, where l indicates which number is smaller, e indicates equality, and g indicates the greater number.

types of comparators

depending on the number of bits, the following are some main types of comparators used in digital circuits −

1-bit magnitude comparator
2-bit magnitude comparator
4-bit magnitude comparator

let us discuss each type of comparator in detail.

1-bit magnitude comparator

a 1-bit magnitude comparator is a logic circuit which can compare two binary numbers of one bit each. it produces an output that indicates the relationship between the two input numbers.

in other words, a 1-bit magnitude comparator is one that compares two 1-bit binary numbers and generates an output showing whether one number is equal to or greater than or less than the other.

the block diagram of a 1-bit magnitude comparator is shown in the following figure −

here, a and b are the 1-bit input numbers, and l, e, and g are the output lines indicating less than or equal to or greater than relationship between a and b respectively.

let us understand the working this type of comparator.

if a = 0 and b = 0 or if a = 1 and b = 1, then a = b. it indicates that the two binary numbers are equal. therefore,

$$\mathrm{e \: = \: \overline{a} \: \cdot \: \overline{b} \: + \: a \: \cdot \: b \: = \: a \: \odot \: b}$$

if a = 0 and b = 1, then a < b. this indicates that the binary number a is less than the binary number b. therefore,

$$\mathrm{l \: = \: \overline{a} \: b}$$

if a = 1 and b = 0, then a > b. it indicates that the binary number a is greater than the binary number b. therefore,

$$\mathrm{g \: = \: a \: \overline{b}}$$

the 1-bit magnitude comparator compares the corresponding bits of the input numbers a and b. for this, it uses different types of logic gates.

the truth table of the 1-bit magnitude comparators is given below −

inputs		outputs
a	b	l (a < b)	e (a = b)	g (a > b)
0	0	0	1	0
0	1	1	0	0
1	0	0	0	1
1	1	0	1	0

we can use this truth table to obtain the boolean expression of the 1-bit magnitude comparator.

$$\mathrm{l \: = \: \overline{a} \: b}$$

$$\mathrm{e \: = \: \overline{a} \: \cdot \: \overline{b} \: + \: a \: \cdot \: b \: = \: a \: \odot \: b}$$

$$\mathrm{g \: = \: a \: \overline{b}}$$

the logic circuit diagram of the 1-bit magnitude comparator is shown in the following figure.

it consists of two and gates, two not gate, and an xnor gate.

2-bit magnitude comparator

a digital combinational circuit used to compare the magnitudes of two 2-bit binary numbers and determine the relationship between them is called a 2-bit magnitude comparator.

hence, the 2-bit magnitude comparator compares the values represented by two 2-bit binary numbers and then generates an output that indicates whether one number is equal to or greater than or less than the other.

the block diagram of a typical 2-bit magnitude comparator is shown in the following figure −

here, the lines a₀a₁ and b₀b₁ represents two 2-bit binary number inputs and the lines l, e, and g represents the less than, equal to, and greater than output lines.

we can understand the operation of the 2-bit magnitude comparator with the help of its truth table given below −

inputs				outputs
a₁	a₀	b₁	b₀	l (a < b)	e (a = b)	g (a > b)
0	0	0	0	0	1	0
0	0	0	1	1	0	0
0	0	1	0	1	0	0
0	0	1	1	1	0	0
0	1	0	0	0	0	1
0	1	0	1	0	1	0
0	1	1	0	1	0	0
0	1	1	1	1	0	0
1	0	0	0	0	0	1
1	0	0	1	0	0	1
1	0	1	0	0	1	0
1	0	1	1	1	0	0
1	1	0	0	0	0	1
1	1	0	1	0	0	1
1	1	1	0	0	0	1
1	1	1	1	0	1	0

let us now derive the boolean expression for the outputs l, e, and g.

case 1: a = b

the comparator produces an output a = b which is e, if a₀ = b₀ and a₁ = b₁. therefore, the boolean expression for the output e will be,

$$\mathrm{e \: = \: (a_{0} \: \odot \: b_{0}) \: (a_{1} \: \odot \: b_{1})}$$

case 2: a < b

the comparator produces an output a < b which is l, if

a₁ = 0 and b₁ = 1, or
a₁ = b₁ and a₀ = 0 and b₀ = 1.

from these statements, we can write the boolean expression for the output l as follows −

$$\mathrm{l \: = \: \overline{a_{1}} \: b_{1} \: + \: (a_{1} \: \odot \: b_{1}) \: \overline{a_{0}} \: b_{0}}$$

case 3: a > b

the output of the comparator will be a > b i.e., g, if

a₁ = 1 and b₁ = 0, or
a₁ = b₁ and a₀ = 1 and b₀ = 0.

from these statements, the boolean expression for the output g will be,

$$\mathrm{g \: = \: a_{1} \: \overline{b_{1}} \: + \: (a_{1} \: \odot \: b_{1}) \: a_{0} \: \overline{b_{0}}}$$

the following figure shows the logic circuit diagram of the 2-bit magnitude comparator −

4-bit magnitude comparator

the 4-bit magnitude comparator is used in more complex digital circuits like microprocessors, microcontrollers, and many more.

it is a type of comparator that can compare the values or magnitudes of two 4-bit binary numbers and produce an output indicating whether one number is equal to or less than or greater than the other.

the block diagram of the 4-bit magnitude comparator is shown in the following figure −

let us now understand the working of this 4-bit magnitude comparator. for that consider a = a₃a₂a₁a₀ is the first 4-bit binary number and b = b₃b₂b₁b₀ is the second 4-bit binary number.

the comparator will show the results as follows −

case 1: a = b

the comparator will produce an output a = b which is e, if all the corresponding bits in the two numbers are equal i.e., a₃ = b₃ and a₂ = b₂ and a₁ = b₁ and a₀ = b₀.

in this case, the boolean expression of the output will be,

$$\mathrm{e \: = \: (a_{3} \: \odot \: b_{3}) \: (a_{2} \: \odot \: b_{2}) \: (a_{1} \: \odot \: b_{1}) \: (a_{0} \: \odot \: b_{0})}$$

case 2: a < b

the comparator will produce an output a < b which is l, if

a₃ = 0 and b₃ = 1, or
a₃ = b₃ and if a₂ = 0 and b₂ = 1, or
a₃ = b₃ and if a₂ = b₂ and if a₁ = 0 and b₁ = 1, or
a₃ = b₃ and if a₂ = b₂ and if a₁ = b₁ and if a₀ = 0 and b₀ = 1.

from these statements, we can derive the boolean expression for the output l, which is given below.

$$\mathrm{l \: = \: \overline{a_{3}} \: b_{3} \: + \: (a_{3} \: \odot \: b_{3}) \: \overline{a_{2}} \: b_{2} \: + \: (a_{3} \: \odot \: b_{3}) \: (a_{2} \: \odot \: b_{2}) \: \overline{a_{1}} \: b_{1} \: + \: (a_{3} \: \odot \: b_{3}) \: (a_{2} \: \odot \: b_{2}) \: (a_{1} \: \odot \: b_{1}) \: \overline{a_{0}} \: b_{0}}$$

case 3: a > b

the comparator produces an output a > b which is g, if

a₃ = 1 and b₃ = 0, or
a₃ = b₃ and if a₂ = 1 and b₂ = 0, or
a₃ = b₃ and if a₂ = b₂ and if a₁ = 1 and b₁ = 0, or
a₃ = b₃ and if a₂ = b₂ and if a₁ = b₁ and if a₀ = 1 and b₀ = 0.

hence, from these statements, we can write the boolean expression for the output g which is,

$$\mathrm{g \: = \: a_{3} \: \overline{b_{3}} \: + \: (a_{3} \: \odot \: b_{3}) \: a_{2} \: \overline{b_{2}} \: + \: (a_{3} \: \odot \: b_{3}) \: (a_{2} \: \odot \: b_{2}) \: a_{1} \: \overline{b_{1}} \: + \: (a_{3} \: \odot \: b_{3}) \: (a_{2} \: \odot \: b_{2}) \: (a_{1} \: \odot \: b_{1}) \: a_{0} \: \overline{b_{0}}}$$

the logic circuit implementation of the 4-bit magnitude comparator is shown in the following figure −

comparator ic

a comparator ic is an integrated circuit which is designed to compare two binary numbers and produce an output based on the comparison results.

a commonly used comparator ic is ic 7485 which is a 4-bit magnitude comparator ic. it is widely in digital electronic applications to compare two 4-bit binary numbers.

the ic 7485 compares corresponding bits of the two input numbers and determines whether one number is equal to or greater than or less than the other. the pin diagram of the ic 7485 is depicted in the following figure.

this ic is widely used in various digital circuits such as microprocessors, microcontrollers, control systems, and arithmetic logic units.

applications of comparators

the comparators are fundamental components in various digital circuits. they provide capabilities to compare voltage levels and make decisions.

some of the key applications of comparators in the field of digital electronics are listed below −

comparators are used to detect changes in voltage levels in electronic circuits.
comparators are also used temperature monitoring systems.
comparators are used as zero-crossing detector in various power circuits like phase control circuits, motor and power control circuits, etc.
comparators are key components in analog to digital converters (adcs).
in signal conditioning circuits, the comparators are used for amplification and filtering of signals before processing.

conclusion

in conclusion, a comparator is a combinational logic circuit used in various digital electronic applications to compare two similar quantities like two 2-bit binary numbers or two voltage levels, etc.

comparators help us to make decisions based on a comparison of two input values. they are widely used in several different electronic devices and systems such as arithmetic logic units, microprocessor-based systems, control systems, automation systems, and telecommunication systems.

depending on the number of input bits required for a particular application, we can design a 1-bit, 2-bit, or 4-bit comparator. also, comparators are available in the form of integrated circuit. the most commonly used ic comparator is ic 7485 which is a 4-bit magnitude comparator.

an encoder is a combinational logic circuit that is used to convert a normal or familiar information into a coded format. in other words, an encoder is a digital device that coverts a piece of information represented in the form of decimal digits and alphabetic characters into a coded form like binary representation. the operation that the encoder performs is termed as encoding.

in this chapter, we will explain the basics of encoder and commonly used types of encoders.

what is an encoder?

an encoder is a digital combinational circuit that converts a human friendly information into a coded format for processing using machines. in simple words, an encoder converts a piece of information normal form to coded form. this process is called encoding.

encoders are crucial components in various digital electronics applications such as data transmission, controlling and automation, communication, signal processing, etc.

an encoder consists of a certain number of input and output lines. where, an encoder can have maximum of "2ⁿ" input lines whereas "n" output lines. hence, an encoder encodes information represented by "2ⁿ" input lines with "n" bits.

the block diagram of an encoder is shown in the following figure −

let us now discuss different types of encoders commonly used in digital electronic applications.

types of encoders

some of the commonly used types of encoders in digital electronics −

4 to 2 encoder
8 to 3 encoder (octal encoder)
decimal to bcd encoder

let us now discuss these three types of most commonly used encoders in detail.

4 to 2 encoder

a 4 to 2 encoder is a type of encoder which has 4 (2²) input lines and 2 output lines. it produces an output code (i.e., convert input information in a 2-bit format) depending on the combination of input lines.

the block diagram of a 4 to 2 encoder is shown in the following figure.

the working of a 4 to 2 encoder for different input combinations is described in the following truth table −

inputs				outputs
i₃	i₂	i₁	i₀	y₁	y₀
0	0	0	1	0	0
0	0	1	0	0	1
0	1	0	0	1	0
1	0	0	0	1	1

from this truth table, we can derive the boolean expression for each output of the 4 to 2 encoder as follows −

$$\mathrm{y_{0} \: = \: i_{1} \: + \: i_{3}}$$

$$\mathrm{y_{1} \: = \: i_{2} \: + \: i_{3}}$$

it is clear that we can implement the logic circuit of the 4 to 2 encoder using two or gates. the following figure depicts the logic diagram of the 4 to 2 encoder.

applications of 4 to 2 encoder

the 4 to 2 encoder is widely used in the following applications: data multiplexing, generating digital control signals, address decoding applications, encoding data in digital systems, etc.

octal to binary encoder

the octal to binary encoder is a type of encoder that converts an octal code into binary code. it accepts 8 input lines and produces a 3-bit output depending on the combination of input lines. therefore, it is also known as 8 to 3 encoder.

the block diagram of an octal to binary encoder is shown in the following figure −

the following truth table describes the working of an octal to binary encoder −

inputs								outputs
i₇	i₆	i₅	i₄	i₃	i₂	i₁	i₀	y₂	y₁	y₀
0	0	0	0	0	0	0	1	0	0	0
0	0	0	0	0	0	1	0	0	0	1
0	0	0	0	0	1	0	0	0	1	0
0	0	0	0	1	0	0	0	0	1	1
0	0	0	1	0	0	0	0	1	0	0
0	0	1	0	0	0	0	0	1	0	1
0	1	0	0	0	0	0	0	1	1	0
1	0	0	0	0	0	0	0	1	1	1

from this truth table, we can write the boolean expression for the outputs of the octal to binary encoder as follows.

$$\mathrm{y_{0} \: = \: i_{1} \: + \: i_{3} \: + \: i_{5} \: + \: i_{7}}$$

$$\mathrm{y_{1} \: = \: i_{2} \: + \: i_{3} \: + \: i_{6} \: + \: i_{7}}$$

$$\mathrm{y_{2} \: = \: i_{4} \: + \: i_{5} \: + \: i_{6} \: + \: i_{7}}$$

from these expressions, it is clear that the implementation of an octal to binary encoder requires 3 or gates.

the logic circuit diagram of the octal to binary encoder is shown in the following figure −

applications of octal to binary encoder

the octal to binary encoder is used in the following applications −

data conversion in digital systems.
conversion of octal memory addresses into binary memory addresses.
in microprocessors and microcontrollers, to convert octal instructions into binary format.
in communication systems, to encode octal data into binary form for transmission, etc.

decimal to bcd encoder

a type of encoder that can convert a decimal number or information represented using decimal number into its equivalent binary-coded decimal (bcd) format is known as a decimal to bcd encoder.

in the bcd encoding scheme, each decimal digit can be converted into a 4-bit binary representation. the following table shows the bcd equivalents of decimal digital from 0 to 9.

decimal digit	bcd code
0	0	0	0	0
1	0	0	0	1
2	0	0	1	0
3	0	0	1	1
4	0	1	0	0
5	0	1	0	1
6	0	1	1	0
7	0	1	1	1
8	1	0	0	0
9	1	0	0	1

the decimal to bcd encoder accepts 10 input lines and produces a 4-bit bcd output depending on the combination of input lines. therefore, sometimes it is also called a 10 to 4 encoder.

the following illustration depicts the block diagram of a decimal to bcd encoder.

the truth table describing the working of the decimal to bcd encoder is given blow −

inputs										outputs
d₉	d₈	d₇	d₆	d₅	d₄	d₃	d₂	d₁	d₀	y₃	y₂	y₁	y₀
0	0	0	0	0	0	0	0	0	1	0	0	0	0
0	0	0	0	0	0	0	0	1	0	0	0	0	1
0	0	0	0	0	0	0	1	0	0	0	0	1	0
0	0	0	0	0	0	1	0	0	0	0	0	1	1
0	0	0	0	0	1	0	0	0	0	0	1	0	0
0	0	0	0	1	0	0	0	0	0	0	1	0	1
0	0	0	1	0	0	0	0	0	0	0	1	1	0
0	0	1	0	0	0	0	0	0	0	0	1	1	1
0	1	0	0	0	0	0	0	0	0	1	0	0	0
1	0	0	0	0	0	0	0	0	0	1	0	0	1

from this truth table, we can write the boolean expression of the decimal to bcd encoder as follows.

$$\mathrm{y_{0} \: = \: d_{1} \: + \: d_{3} \: + \: d_{5} \: + \: d_{7} \: + \: d_{9}}$$

$$\mathrm{y_{1} \: = \: d_{2} \: + \: d_{3} \: + \: d_{6} \: + \: d_{7}}$$

$$\mathrm{y_{2} \: = \: d_{4} \: + \: d_{5} \: + \: d_{6} \: + \: d_{7}}$$

$$\mathrm{y_{3} \: = \: d_{8} \: + \: d_{9}}$$

the logic circuit of the decimal to bcd encoder can be implemented using four or gates which is shown in the following figure −

applications of decimal to bcd encoder

decimal to bcd encoders find their application in digital clocks and timers, data processing devices and storage systems, calculators, measuring instruments, display devices, microprocessors, microcontrollers, embedded systems, etc.

conclusion

an encoder converts a piece of information in a certain coded format. encoders are essential elements in various digital systems such as automation and control systems, communication systems and storage units, computing and calculating devices, measuring instruments, data converters, and more.

in this chapter, we covered the most widely used types of encoders, they are 4 to 2 encoder, octal to binary encoder, and decimal to bcd encoder.

a keyboard encoder is an electronic device used in computer peripherals, mainly in keyboards, to convert keystrokes into digital signals. in this chapter, we will discuss the definition, types, and applications of keyboard encoders. lets start with the basic introduction to keyboard encoders.

what is a keyboard encoder?

an electronic circuit which is used to translate keystrokes from physical keyboards into digital signals that a processing device can understand and process is known as a keyboard encoder. it is basically a type of encoder that encodes the information represented in alphanumeric form into digital or binary form.

a keyboard encoder acts as an interface between the physical keyboard and the processing unit of a computing system. the primary function of a keyboard encoder is to detect the key presses and encode them into binary format. this encoded signal is then sent to the processing system through a communication interface like usb, bluetooth, etc.

keyboard encoders are essential components in input devices like keyboards as they allow conversion of human data in machine language.

applications of keyboard encoders

keyboard encoders are mainly used in input devices like keyboards to convert physical keystrokes into digital signals that a processing device can process.

here are some examples of applications of keyboard encoders −

keyboards used in desktop computers and laptops.
keyboard encoders are also used in gaming peripherals like gaming keyboards.
keyboard encoders are also used in control panels and human-machine interfaces used in industrial control systems and automation equipment.
keyboard encoders are also equipped in various medical devices such as medical imaging devices, patient monitoring devices, diagnostic systems, etc.
keyboard encoders are also important components in point-of-sales (pos) devices.
keyboard encoders are utilized in data entry devices like scanners, handheld devices, etc.

keyboard encoders are essential component in input devices allowing users to input data into a processing system. they create an interface between the input hardware and digital processing unit. the above section highlights some common examples where the keyboard encoders are used.

let us understand the circuit and working of a typical 8421 bcd keyboard encoder which is an important element in various keyboard designs. the 8421 bcd keyboard encoder provides a simple and efficient way of encoding decimal digit into binary format for processing using digital systems like microcontrollers.

8421 bcd keyboard encoder

the 8421 bcd keyboard encoder is a type of encoder used in keyboards and many other digital devices where decimal digits are need to be converted into a binary format or bcd (binary-coded decimal).

the diode matrix of the 8421 bcd keyboard encoder is shown in the following figure −

this keyboard encoder uses sr flip-flops to store the bcd output bits designated as q₈q₄q₂q₁.

when a key corresponding to any decimal digit between "0" and "9" is pressed, the power supply v_cc turns on the appropriate diodes which are further connected to the set (s) and reset (r) inputs of the flip-flops.

in this circuit, all the diodes are connected in a manner that each sr flip-flop set or reset to produce a combination of 4-bits representing the corresponding decimal digit in bcd format.

let us take an example to understand the working of this 8421 bcd keyboard encoder.

when we press the key "0", the diodes connected to the r inputs of the flip-flops q₈, q₄, q₂, and q₁ are forward biased. hence, the output will be 0000.

similarly, when we press the key "3", the diodes connected to the r inputs of q₈ and q₄ are forward biased and the diodes connected to the s inputs of q₂ and q₁ are forwards. hence, this produces an output as 0011.

the keyboard encoder also works in the same way for all other decimal digits.

conclusion

in this chapter, we explained the functions and applications of keyboard encoder. also, we highlighted the construction and working of a simple 8421 bcd keyboard encoder which is used in various small electronic devices like atms, pos terminals, mobile phones, and many other electronic devices.

in digital electronics, an encoder is a combinational logic circuit which accepts inputs as decimal digits and alphabetic characters, and produces the outputs as the coded representation of the inputs. in other words, an electronic combinational circuit that converts numbers and symbols into their corresponding coded format is called an encoder. the operation performed by the encoder is called encoding which is a process of converting familiar numbers and characters into their equivalent codes.

an encoder has 2ⁿ input lines and n-output lines. at a time, only one of the 2ⁿ input lines is activated. the coded output of the encoder depends upon the activated input line. there are several types of encoders available such as "octal to binary encoder", "decimal to bcd encoder", "keyboard encoders", etc.

what is a priority encoder?

in case of an ordinary encoder, one and only one decimal input can be activated at any given time. but in the case of some practical digital systems, two or more decimal inputs can unintentionally become active at the same time that might cause a confusion. for example, on a keyboard, a user presses key 4 before releasing another key 2. in such a situation, the output will be corresponding to (6)₁₀, instead of being (4)₁₀ or (2)₁₀. this kind of problems can be solved with the help of priority encoder.

in digital electronics, a combinational logic circuit which produces outputs in response to only one input among all those that may be activated at the same time is called a priority encoder. for this, it uses a priority system, and hence it is named so.

one most popular priority system used is based on the relative magnitudes of the inputs. according to the priority system, the decimal input having largest magnitude among all the simultaneous inputs is encoded. hence, as per this priority encoding system, the priority encoder would encode 4 if both 4 and 2 are active at the same time.

in some practical systems, priority encoders have several inputs which are routinely active at the same time. in such cases, the primary function of the encoder is to select the input with the highest priority. this function of the priority encoder is known as arbitration. for example, in a computer system, multiple input devices are connected, and several of them may try to supply data to the system at the same time. in this case, the priority encoder is responsible for enabling that input device which has the highest priority among all the input devices.

types of priority encoders

several types of priority encoders are there. some most important types of priority encoders are listed and explained below.

4 input priority encoder
decimal to bcd priority encoder
octal to binary priority encoder

let us discuss each type of priority encoder in detail.

4-input priority encoder

the logic circuit of the 4-input priority encoder is shown in figure-1.

it has three outputs designated by a, b, and v. where, a and b are the ordinary outputs and v is the output that acts as a valid bit indicator. this third output v is set to 1 when one or more inputs are equal to 1. in the case, when all the inputs to the encoder are equal to 0, there is no any valid input, and thus the output v is set to 0. the other two outputs, i.e. a and b of the encoder are not determined when v is equal to 0. therefore, when, v is equal to 0, the outputs a and b are specified as "dont care conditions".

the truth table of the 4-input priority encoder is shown below.

inputs (x = dont care)				outputs
i₀	i₁	i₂	i₃	a	b	v
0	0	0	0	x	x	0
1	0	0	0	0	0	1
x	1	0	0	0	1	1
x	x	1	0	1	0	1
x	x	x	1	1	1	1

from this truth table, it can be observed that the higher the subscript number of the input, the higher the priority of the input. thus, the input i₃ has the highest priority. therefore, regardless of the values of other inputs, when the input i₃ is equal to 1, the output for ab is 11, i.e. 3. the input i₂ has the next lower priority, and then i₁, and finally i₀ has the lowest priority.

we can write the boolean expression for outputs a, b, and v from the above table as follows,

$$\mathrm{a \: = \: i_{3} \: + \: \bar{i_{3}} \: i_{2}\: = \: i_{3} \: + \: i_{2}}$$

$$\mathrm{b \: = \: i_{3} \: + \: \bar{i_{3}} \: \bar{i_{2}} \: i_{1} \: = \: i_{3} \: + \: \bar{i_{2}} \: i_{1}}$$

and,

$$\mathrm{v \: = \: i_{3} \: + \: i_{2} \: + \: i_{1} \: + \: i_{0}}$$

hence, the condition for the output v is an or operation of all the input variables.

decimal to bcd priority encoder

this type of priority encoder performs the function of encoding the decimal digits into 4-bit bcd (binary coded decimal) outputs. as it is a decimal to bcd priority encoder, therefore, it produces a bcd corresponding to the decimal digit of highest priority among all the inputs and ignores all others.

the truth table of the decimal to bcd priority encoder is given below.

decimal inputs (x = dont care)									bcd outputs
i₁	i₂	i₃	i₄	i₅	i₆	i₇	i₈	i₉	a₃	a₂	a₁	a₀
1	1	1	1	1	1	1	1	1	1	1	1	1
x	x	x	x	x	x	x	x	0	0	1	1	0
x	x	x	x	x	x	x	0	1	0	1	1	1
x	x	x	x	x	x	0	1	1	1	0	0	0
x	x	x	x	x	0	1	1	1	1	0	0	1
x	x	x	x	0	1	1	1	1	1	0	1	0
x	x	x	0	1	1	1	1	1	1	0	1	1
x	x	0	1	1	1	1	1	1	1	1	0	0
x	0	1	1	1	1	1	1	1	1	1	0	1
0	1	1	1	1	1	1	1	1	1	1	1	0

the truth table of the decimal to bcd priority encoder clearly shows that the magnitudes of the decimal inputs determine their priorities. if any decimal input is high, it will be encoded if all other higher value inputs are low regardless of the state of all lower value inputs.

octal to binary priority encoder

this type of priority encoder is used to perform encoding of octal code into binary code. hence, this type priority encoder has eight inputs and three outputs that produce corresponding binary code as given in the truth table below.

inputs								outputs
i₀	i₁	i₂	i₃	i₄	i₅	i₆	i₇	a₂	a₁	a₀	v
0	0	0	0	0	0	0	0	x	x	x	0
1	0	0	0	0	0	0	0	0	0	0	1
x	1	0	0	0	0	0	0	0	0	1	1
x	x	1	0	0	0	0	0	0	1	0	1
x	x	x	1	0	0	0	0	0	1	1	1
x	x	x	x	1	0	0	0	1	0	0	1
x	x	x	x	x	1	0	0	1	0	1	1
x	x	x	x	x	x	1	0	1	1	0	1
x	x	x	x	x	x	x	1	1	1	1	1

this is all about the priority encoder and its major types in digital electronics.

what is a decoder?

in digital electronics, a combinational logic circuit that converts an n-bit binary input code into m output channels in such a way that only one output channel is activated for each one of the possible combinations of inputs is known as a decoder.

in other words, a combinational logic circuit which converts n input lines into a maximum of 2_n output lines is called a decoder.

therefore, a decoder is a combination logic circuit that is capable of identifying or detecting a particular code. the operation that a decoder performs is referred to as decoding. a general block diagram of a decoder is shown in figure-1.

here, the decoder has n input lines and m (2ⁿ) output lines. in a decoder, each of the n input lines can be a 0 or a 1, hence the number of possible input combinations or codes be equal to 2ⁿ. for each of these input combinations, only one of the m output lines will be active, and all other output lines will remain inactive.

types of decoders

there are several types of decoder present. but, based on the input and output lines present, decoders may classified into the following three types −

2 to 4 decoder
3 to 8 decoder
4 to 16 decoder

now, let us discuss each type of decoder in detail one by one.

2 to 4 decoder

the 2 to 4 decoder is one that has 2 input lines and 4 (2²) output lines. the functional block diagram of the 2 to 4 decoder is shown in figure-2.

when this decoder is enabled with the help of enable input e, then its one of the four outputs will be active for each combination of inputs. the operation of this 2-line to 4-line decoder can be analyzed with the help of its truth table which is given below.

inputs			outputs
e	a	b	y₃	y₂	y₁	y₀
0	x	x	0	0	0	0
1	0	0	0	0	0	1
1	0	1	0	0	1	0
1	1	0	0	1	0	0
1	1	1	1	0	0	0

using this truth table, we can derive the boolean expression for each output as follows −

$$\mathrm{y_{0} \: = \: e \: \cdot \: \bar{a} \: \cdot \: \bar{b}}$$

$$\mathrm{y_{1} \: = \: e \: \cdot \: \bar{a} \: \cdot \: b}$$

$$\mathrm{y_{2} \: = \: e \: \cdot \: a \: \cdot \: \bar{b}}$$

$$\mathrm{y_{3} \: = \: e \: \cdot \: a \: \cdot \: b}$$

as each output term contains products of input variables that can be implemented with the help of and gates. therefore, the logic circuit diagram of the 2 to 4 decoder is shown in figure-3.

operation

the operation of logic circuit of the 2 to 4 decoder is described as follows −

when enable input (e) is inactive, i.e. set to 0, none of the and gates will function.
when enable input (e) is made active by setting it to 1, then the circuit works as explained below.
when a = 0 and b = 0, the and gate 1 becomes active and produces output y₀.
when a = 0 and b = 1, the and gate 2 becomes active and produces output y₁.
when a = 1 and b = 0, the and gate 3 becomes active and produces output y₂.
when a = 1 and b = 1, the and gate 4 becomes active and produces output y₃.

3 to 8 decoder

the 3 to 8 decoder is one that has 3 input lines and 8 (2³) output lines. the functional block diagram of the 3 to 8 decoder is shown in figure-4.

when this decoder is enabled with the help of enable input e, then it's one of the eight outputs will be active for each combination of inputs. the operation of this 3-line to 8-line decoder can be analyzed with the help of its function table which is given below.

inputs				outputs
e	a	b	c	y₇	y₆	y₅	y₄	y₃	y₂	y₁	y₀
0	x	x	x	0	0	0	0	0	0	0	0
1	0	0	0	0	0	0	0	0	0	0	1
1	0	0	1	0	0	0	0	0	0	1	0
1	0	1	0	0	0	0	0	0	1	0	0
1	0	1	1	0	0	0	0	1	0	0	0
1	1	0	0	0	0	0	1	0	0	0	0
1	1	0	1	0	0	1	0	0	0	0	0
1	1	1	0	0	1	0	0	0	0	0	0
1	1	1	1	1	0	0	0	0	0	0	0

using this function table, we can derive the boolean expression for each output as follows −

$$\mathrm{y_{0} \: = \: e \: \bar{a} \: \bar{b} \: \bar{c}}$$

$$\mathrm{y_{1} \: = \: e \: \bar{a} \: \bar{b} \: c}$$

$$\mathrm{y_{2} \: = \: e \: \bar{a} \: b \: \bar{c}}$$

$$\mathrm{y_{3} \: = \: e \: \bar{a} \: b \: c}$$

$$\mathrm{y_{4} \: = \: e \: a \: \bar{b} \: \bar{c}}$$

$$\mathrm{y_{5} \: = \: e \: a \: \bar{b} \: c}$$

$$\mathrm{y_{6} \: = \: e \: a \: b \: \bar{c}}$$

$$\mathrm{y_{7} \: = \: e \: a \: b \: c}$$

as we can see, each output term contains products of input variables, hence they can be implemented with the help of and gates. therefore, the logic circuit diagram of the 3 to 8 decoder is shown in figure-5.

operation

the operation of logic circuit of the 3 to 8 decoder is described as follows −

when enable input (e) is inactive, i.e. set to 0, none of the and gates will function.
when enable input (e) is made active by setting it to 1, then the circuit works as described below.
when a = 0, b = 0, and c = 0, the and gate 1 becomes active and produces output y₀.
when a = 0, b = 0, and c = 1, the and gate 2 becomes active and produces output y₁.
when a = 0, b = 1, and c = 0, the and gate 3 becomes active and produces output y₂.
when a = 0, b = 1, and c = 1, the and gate 4 becomes active and produces output y₃.
when a = 1, b = 0, and c = 0, the and gate 5 becomes active and produces output y₄.
when a = 1, b = 0, and c = 1, the and gate 6 becomes active and produces output y₅.
when a = 1, b = 1, and c = 0, the and gate 7 becomes active and produces output y₆.
when a = 1, b = 1, and c = 1, the and gate 8 becomes active and produces output y₇.

4 to 16 decoder

the 4 to 16 decoder is the type of decoder which has 4 input lines and 16 (2¹⁴) output lines. the functional block diagram of the 4 to 16 decoder is shown in figure-6.

when this decoder is enabled with the help of enable input e, it's one of the sixteen outputs will be active for each combination of inputs. the operation of the 4-line to 16-line decoder can be analyzed with the help of its function table which is given below.

inputs					output
e	a	b	c	d	output
0	x	x	x	x	0
1	0	0	0	0	y₀
1	0	0	0	1	y₁
1	0	0	1	0	y₂
1	0	0	1	1	y₃
1	0	1	0	0	y₄
1	0	1	0	1	y₅
1	0	1	1	0	y₆
1	0	1	1	1	y₇
1	1	0	0	0	y₈
1	1	0	0	1	y₉
1	1	0	1	0	y₁₀
1	1	0	1	1	y₁₁
1	1	1	0	0	y₁₂
1	1	1	0	1	y₁₃
1	1	1	1	0	y₁₄
1	1	1	1	1	y₁₅

from this function table, we can directly write the boolean expression for each output as follows −

$$\mathrm{y_{0} \: = \: e \: \bar{a} \: \bar{b} \: \bar{c} \: \bar{d}}$$

$$\mathrm{y_{1} \: = \: e \: \bar{a} \: \bar{b} \: \bar{c} \: d}$$

$$\mathrm{y_{2} \: = \: e \: \bar{a} \: \bar{b} \: c \: \bar{d}}$$

$$\mathrm{y_{3} \: = \: e \: \bar{a} \: \bar{b} \: c \: d}$$

$$\mathrm{y_{4} \: = \: e \: \bar{a} \: b \: \bar{c} \: \bar{d}}$$

$$\mathrm{y_{5} \: = \: e \: \bar{a} \: b \: \bar{c} \: d}$$

$$\mathrm{y_{6} \: = \: e \: \bar{a} \: b \: c \: \bar{d}}$$

$$\mathrm{y_{7} \: = \: e \: \bar{a} \: b \: c \: d}$$

$$\mathrm{y_{8} \: = \: e \: a \: \bar{b} \: \bar{c} \: \bar{d}}$$

$$\mathrm{y_{9} \: = \: e \: a \: \bar{b} \: \bar{c} \: d}$$

$$\mathrm{y_{10} \: = \: e \: a \: \bar{b} \: c \: \bar{d}}$$

$$\mathrm{y_{11} \: = \: e \: a \: \bar{b} \: c \: d}$$

$$\mathrm{y_{12} \: = \: e \: a \: b \: \bar{c} \: \bar{d}}$$

$$\mathrm{y_{13} \: = \: e \: a \: b \: \bar{c} \: d}$$

$$\mathrm{y_{14} \: = \: e \: a \: b \: c \: \bar{d}}$$

$$\mathrm{y_{15} \: = \: e \: a \: b \: c \: d}$$

we can implement these output expression in the same way as we done for the 2 to 4 decoder and 3 to 8 decoder.

now, let us discuss the applications of decoders.

applications of decoders

decoders are used in the cases where an output or a collection of outputs is to be activated only on the occurrence of a particular combination of input codes. some important applications of decoders are listed below −

decoders are used for code conversions.
decoders are extensively used in memory systems of computers.
decoders are also used for de-multiplexing or data distribution.
decoders are also used in data routing applications where very short propagation delay is required.
decoder may also be used for timing or sequencing purposes.
decoders are also utilized to turn on and off digital devices at a specific time.

this is all about decoder and its applications in digital electronic systems.

what is a demultiplexer?

a demultiplexer is a combinational logic circuit that accepts a single input and distributes it over several output lines. demultiplexer is also termed as demux in short. as demultiplexer is used to transmit the same data to different destinations, hence it is also known as data distributor.

there is another combinational logic circuit named multiplexer which performs opposite operation of the demultiplexer, i.e. accepts several inputs and transmits one of them at time to the output line.

from the definition, we can state that a demultiplexer is a 1-to-2ⁿ device. the functional block diagram of a typical 1×2ⁿ demultiplexer is shown in figure-1.

it can be seen that the demultiplexer has only one data input line, 2ⁿ output lines, and n select lines. the logic level applied to select lines of the demultiplexer determines the output channel to which the input data will be transmitted.

demultiplexer circuit are the combinational logic circuit widely used in digital decoders and boolean function generator circuits.

types of demultiplexer

based on the number of output lines (2ⁿ), demultiplexers can be classified into several types. some commonly used types of demultiplexers are −

1×2 demultiplexer
1×4 demultiplexer

now, let us briefly discuss each type of demultiplexer.

1×2 demultiplexer

the functional block diagram of a 1×2 demultiplexer is shown in figure-2.

the 1×2 demultiplexer consists of 1 input line (i), 1 select line (s), and 2 output lines (y₀ and y₁). the logic level applied at the select line determines the output line to which the input data will be transmitted.

the operation of the 1×2 demultiplexer can be analyzed with the help of its function table given below.

select line	outputs
s	y₁	y₀
0	0	i
1	i	0

from this function table of 1×2 demultiplexer, we can directly derive the boolean expression for each output as follow.

$$\mathrm{y_{0} \: = \: \bar{s} \: i}$$

and,

$$\mathrm{y_{1} \: = \: s \: i}$$

1×4 demultiplexer

the functional block diagram of 1×4 demultiplexer is shown in figure-3.

the 1×4 demultiplexer has 1 input line (i), 2 select line (s₀ and s₁), and 4 output lines (y₀, y₁, y₂, and y₃). the logic level applied to the select lines determines the output line to which the input data (i) will be transmitted.

the operation of the 1×4 demultiplexer can be understood with the help of its function table given below.

select line		outputs
s₁	s₀	y₃	y₂	y₁	y₀
0	0	0	0	0	i
0	1	0	0	i	0
1	0	0	i	0	0
1	1	i	0	0	0

from this truth table of 1×4 demultiplexer, we can directly write the boolean expression for each output as follow.

$$\mathrm{y_{0} \: = \: \bar{s_{1}} \: \bar{s_{0}} \: i}$$

$$\mathrm{y_{1} \: = \: \bar{s_{1}} \: s_{0} \: i}$$

$$\mathrm{y_{2} \: = \: s_{1} \: \bar{s_{0}} \: i}$$

$$\mathrm{y_{3} \: = \: s_{1} \: s_{0} \: i}$$

we can easily understand the operation of the above circuit. similarly, you can implement 1×8 demultiplexer and 1×16 demultiplexer by following the same procedure.

implementation of higher-order demultiplexer

now, let us implement the following two higher-order demultiplexers using lower-order demultiplexers.

1×8 demultiplexer
1×16 demultiplexer

1×8 deultiplexer

in this section, let us implement 1×8 demultiplexer using 1×4 demultiplexers and 1×2 demultiplexer. we know that 1×4 demultiplexer has single input, two selection lines and four outputs. whereas, 1×8 demultiplexer has single input, three selection lines and eight outputs.

so, we require two 1×4 demultiplexers in second stage in order to get the final eight outputs. since, the number of inputs in second stage is two, we require 1×2 demultiplexer in first stage so that the outputs of first stage will be the inputs of second stage. input of this 1×2 demultiplexer will be the overall input of 1×8 demultiplexer.

let the 1×8 demultiplexer has one input i, three selection lines s₂, s₁ & s₀ and outputs y₇ to y₀. the truth table of 1×8 demultiplexer is shown below.

selection inputs			outputs
s₂	s₁	s₀	y₇	y₆	y₅	y₄	y₃	y₂	y₁	y₀
0	0	0	0	0	0	0	0	0	0	i
0	0	1	0	0	0	0	0	0	i	0
0	1	0	0	0	0	0	0	i	0	0
0	1	1	0	0	0	0	i	0	0	0
1	0	0	0	0	0	i	0	0	0	0
1	0	1	0	0	i	0	0	0	0	0
1	1	0	0	i	0	0	0	0	0	0
1	1	1	i	0	0	0	0	0	0	0

we can implement 1×8 demultiplexer using lower order multiplexers easily by considering the above truth table. the block diagram of 1×8 demultiplexer is shown in the following figure.

the common selection lines, s₁ & s₀ are applied to both 1×4 demultiplexers. the outputs of upper 1×4 demultiplexer are y₇ to y₄ and the outputs of lower 1×4 demultiplexer are y₃ to y₀.

the other selection line, s₂ is applied to 1×2 demultiplexer. if s₂ is zero, then one of the four outputs of lower 1×4 demultiplexer will be equal to input, i based on the values of selection lines s₁ & s₀. similarly, if s₂ is one, then one of the four outputs of upper 1×4 demultiplexer will be equal to input, i based on the values of selection lines s₁ & s₀.

1×16 demultiplexer

in this section, let us implement 1×16 demultiplexer using 1×8 demultiplexers and 1×2 demultiplexer. we know that 1×8 demultiplexer has single input, three selection lines and eight outputs. whereas, 1×16 demultiplexer has single input, four selection lines and sixteen outputs.

so, we require two 1×8 demultiplexers in second stage in order to get the final sixteen outputs. since, the number of inputs in second stage is two, we require 1×2 demultiplexer in first stage so that the outputs of first stage will be the inputs of second stage. input of this 1×2 demultiplexer will be the overall input of 1×16 demultiplexer.

let the 1×16 demultiplexer has one input i, four selection lines s₃, s₂, s₁ & s₀ and outputs y₁₅ to y₀. the block diagram of 1×16 demultiplexer using lower order multiplexers is shown in the following figure.

the common selection lines s₂, s₁ & s₀ are applied to both 1×8 demultiplexers. the outputs of upper 1×8 demultiplexer are y₁₅ to y₈ and the outputs of lower 1×8 demultiplexer are y₇ to y₀.

the other selection line, s₃ is applied to 1×2 demultiplexer. if s₃ is zero, then one of the eight outputs of lower 1×8 demultiplexer will be equal to input, i based on the values of selection lines s₂, s₁ & s₀. similarly, if s3 is one, then one of the 8 outputs of upper 1×8 demultiplexer will be equal to input, i based on the values of selection lines s₂, s₁ & s₀.

integrated circuits (ics) working as demultiplexer

demultiplexer can also be built in the form of ics. there are several types of ics available that work as demultiplexer. some common of them are listed below −

74139 ic works as a 1×4 demultiplexer
74237 ic works as a 1×8 demultiplexer
74154 ic works as a 1×16 demultiplexer

advantages of demultiplexer

the important advantages of demultiplexer are given below −

by using demultiplexers, we can increase the efficiency of the communication systems.
demultiplexer can separate different signals from a mixed signal stream.
demultiplexer can decode the signals produced by a multiplexer.

disadvantages of demultiplexer

the major disadvantages of demultiplexers are listed below −

the use of demultiplexer can cause wastage of bandwidth.
the synchronization of signals can create a delay in the system.

applications of demultiplexer

demultiplexer is a crucial combinational logic circuit which is used in a number of applications. some important uses of demultiplexers are listed below −

demultiplexer are used in several input and output devices for data routing.
demultiplexer are used in digital control systems to select one signal from a mutual stream of signals.
demultiplexer are also employed for data transmission in synchronous systems.
demultiplexer are also utilized in data acquisition systems.
demultiplexer can be used for generating boolean functions.
demultiplexer can be used in serial to parallel converters.
demultiplexer are used for broadcasting of atm packets.
demultiplexer can also be used to design automatic test equipment, etc.

this is all about demultiplexer, its types, and applications.

the arithmetic logic unit (alu) is the fundamental component in a computing system like a computer. it is basically the actual data processing element within the central processing unit (cpu) in a computing system. it performs all the arithmetic and logical operations and forms the backbone of modern computer technology.

in this chapter, we will explain the working of the arithmetic logic unit, along with its main components, their functions, and the importance of the alu in the field of digital system designs.

what is arithmetic logic unit?

arithmetic logic unit abbreviated as alu is considered as the engine or heart of every central processing unit (cpu). alu is basically a combination logic circuit that can perform arithmetic and logical operation on digital data (data in binary format). it can also execute instructions given to a computing system like a digital computer.

within the complex architecture of a digital computing system, the arithmetic logic unit or alu plays an important role as it executes and processes all the instructions, performs calculations, manipulates binary data, and performs various decision-making operations.

the development of arithmetic logic unit begins with the need for efficient, high speed, and accurate data processing and computation. with the advancement in electronics technologies, alu has become a highly sophisticated digital data processing device that can handle a large number of complex instructions and computational tasks.

todays alu provides high accuracy, precision, and significantly fast processing speed in computing operations.

features of arithmetic logic unit

here are some key features of arithmetic logic unit −

the alu can perform all arithmetic and logic operations such as addition, subtraction, multiplication, division, logical comparisons, etc.
it can also perform bitwise and mathematical operations on binary numbers.
it contains two segments namely, au (arithmetic unit) and lu (logic unit) to perform arithmetic operations and logical operations respectively.
it is the computational powerhouse within a central processing unit (cpu).
alu is the part of every cpu where actual data processing takes place.
alu is responsible for interpreting the code instructions based on which operations to be performed on the input data.
once the data processing is completed, the alu sends the outcomes to the memory unit or output unit.

main components of arithmetic logic unit

the arithmetic logic unit consists of various functional parts that are responsible for performing specific operations like addition, subtraction, multiplication, division, comparison, and more. some of the key components of the arithmetic logic unit are explained below −

arithmetic unit

the main components used in the arithmetic unit (au) segment of the arithmetic logic unit are as follows −

adder

the adder or binary adder is one of the important components of the arithmetic logic unit. it performs the addition of two or more binary numbers. to accomplish this operation, it performs a series of logical and arithmetic operations. some common types of adders used in the arithmetic ogic unit are half-adder, full-adder, parallel adder, and ripple carry adder. each type of adder is designed and optimized to perform a specific computing operation.

subtractor

the subtractor is another digital combinational circuit designed to perform subtraction of binary numbers. in most arithmetic logic unit, the subtractor uses 2s complement arithmetic to perform subtraction on binary numbers.

multiplier and divider

in more complex and advanced arithmetic logic units, dedicated multiplier and divider circuits are also implemented to perform multiplication and division on binary numbers. these circuits use advanced processing techniques like iterative or parallel processing to accomplish these operations.

logic unit

the logic unit (lu) of the alu comprises the components responsible for performing boolean or comparison operations. the following are some main components of the logic unit of an alu −

logic gates

the logic gates like and, or, not, nand, nor, xor, and xnor are the key components of logic unit. these are standard logic circuits that can manipulate input data based on some predefined logical instructions and generate a desired output.

each logic gate can perform a specific logical operation. however, different types of logic gates can be connected together in a specific manner to perform complex logical operations.

type of logic gate

the brief overview of each type of logic gate is explained here −

and gate − it performs the boolean multiplication on input binary data. its output is logic 1 or true, only when all its inputs are logic 1 or true.
or gate − the or gate performs the boolean addition of input binary data. it generates a logic 1 or true output, if any of its inputs is logic 1 or true.
nor gate − the not gate performs the inversion operation. it gives a logic 1 or true output when its input is logic 0 or false and vice-versa.
nand gate − the nand gate performs the noted and operation and produces a logic 1 or true output when both inputs or any of the inputs is logic 0 or false.
nor gate − the nor gate performs the noted or operation and generates a logic 1 or true output when all its inputs are logic 0 or false.
xor gate − the xor gate performs the exclusive or operation and produces a logic 1 or true output when its both inputs are dissimilar. hence, it is used as inequality detector.
xnor gate − the xnor gate performs the exclusive nor operation and gives a logic 1 or true output when both its inputs are similar. thus, it is used as an equality detector.

this is all about structure and components of the arithmetic logic unit. let us now understand what functions an alu can perform.

functions of arithmetic logic unit

the arithmetic logic unit can perform a wide range of functions and operations in digital computing systems. some important functions that an arithmetic logic unit perform are explained below −

arithmetic operations

the arithmetic operations are one of the primary functions that the arithmetic logic unit performs. this category of operations includes addition, subtraction, multiplication, and division of binary numbers. all these operations form the basis of mathematical computations that the arithmetic logic unit can perform.

logical operations

the arithmetic logic unit can also perform various logical operations such as and operation, or operation, not operation, etc. these logical operations form the basis of decision making and data manipulation processes.

comparison operations

the arithmetic logic unit also facilitates to perform various comparison operations such as equal to, not equal to, less than, greater than, etc. these comparison operations are essential in decision making processes.

shift operations

the arithmetic logic unit can also perform shift operations on binary numbers such as left shift and right shift. these operations are important in multiplication and division operations. the shift operations can manipulate binary data at bit level and hence optimize the arithmetic calculations.

working of arithmetic logic unit

the working of the arithmetic logic unit depends on a combination of input data and control signals. in other words, the arithmetic logic unit receives the input data and control signals and then interpret these data and signals to perform specific operations.

let us understand the working of the arithmetic logic unit in detail by breaking it down in sub-components.

receiving input data and control signals

the arithmetic logic unit receives the input data from the user and a set of control signals that specifies the operation to be performed. the data is received through the input data path while the control signals are received from the control unit.

execution of operation

once the arithmetic logic unit received the input data and control signals, it selects an appropriate functional component among arithmetic unit, logic unit, comparison unit, or shift unit to perform the specific operation. once the operation completes, the alu sends the results to the memory unit for storage or output unit.

significance of arithmetic logic unit

in the field of digital electronics and computing technology, the arithmetic logic unit plays an important role because of the following reasons −

it can perform the arithmetic, logical, and comparison operations with very high accuracy, precision, and efficiency.
it can also perform complex data processing and decision-making operations.
alu can execute complex processing tasks at a very high speed that results in better performance and higher efficiency.
alu introduces versatility as it can execute a wide range of computational tasks.

conclusion

this is all about arithmetic logic unit (alu) which is an important combinational logic circuit in digital electronics and modern computing systems. it acts as the heart of central processing unit (cpu) and executes all kinds of operations including arithmetic, logical, and comparison operations. in a digital computing system, the arithmetic logic unit acts as a primary functional unit that processes the input data based on the instructions. in this chapter, we have studied all the important concepts related to the arithmetic logic unit.

led (light emitting diode) is a semiconductor device that emits either visible light or infrared light when it is forward biased. thus, it is widely used in different electronic devices like tv screens, mobile screens, watches and clocks, remote controls, etc. a light emitting diode (led) basically converts electrical energy into light energy when an electric current flows through it.

in this article, we will discuss an application of led in seven segment display. the seven segment displays are extensively used in in different electronic gadgets like calculators, counters, watches, electronic measuring instruments, etc.

what is a seven segment led display?

seven segment display is an led based display screen that can display information in the form of decimal numbers. the seven segment display is a used in place of the more complex dot matrix displays. it is called so because it consists of seven segments of light emitting diodes (leds) that are assembled like decimal 8 as shown in the following figure.

seven segments led display can be used in applications where an electronic display device is required for showing decimal numbers from 0 to 9, sometimes, basic characters as well. since, it uses leds, therefore it is an energy efficient display device. therefore, it is most widely used in those devices that are powered by a small battery or a cell.

working of seven segment led display

a seven segment display consists of seven led segments arranged like a decimal 8. these led segments are illuminated to form a pattern that represents a decimal number from 0 to 9. now, let us understand, how the seven segment led display work to display different numbers.

when electrical energy is supplied to all the segments, then the seven segment led display shows the decimal number 8.
when power is given to all the segments and if we disconnect power from the segment g, then it displays the decimal number 0.
when the power is given to segments "b" and "c" only, then it displays the number 1.
when the power is given to the segments "a", "b", "g", "e", "d", then it displays the number 2.
when the power is given to segments "a", "b", "g", "c", "d", then it displays the number 3.
when the power is given to segments "b", "c", "f", "g", then it displays the number 4.
when the power is given to segments "a", "c", "d", "f", "g", then it displays the number 5.
when the power is given to segments "a", "c", "d", "e", "f", "g", then it displays the number 6.
when the power is given to segments "a", "b", "c", then it displays the number 7.
when the power is given to segments "a", "b", "c", "d", "f", "g", then it displays the number 9.

in this way, we can display any decimal number from 0 to 9 by illuminating a set of led segments of the seven segment led display.

truth table of seven segment led display

the following table shows the truth table of a seven segment led display to display the decimal numbers from 0 to 9.

seven segment display output	led segments inputs
seven segment display output	a	b	c	d	e	f	g
0	1	1	1	1	1	1	0
1	0	1	1	0	0	0	0
2	1	1	0	1	1	0	1
3	1	1	1	1	0	0	1
4	0	1	1	0	0	1	1
5	1	0	1	1	0	1	1
6	1	0	1	1	1	1	1
7	1	1	1	0	0	0	0
8	1	1	1	1	1	1	1
9	1	1	1	1	0	1	1

types of seven segment led displays

there are two types of seven segment displays available −

common cathode seven segment display

in this type of seven segment display, the cathode terminal of all led segments are connected together to logic 0 (lower voltage level). the logic 1 (higher voltage level) is applied through a current limiting resistor to forward bias the individual led segments at their anode terminals.

common anode seven segment display

in this type of seven segment led display, the anode terminals of all the led segments are connected together to the logic 1 (higher voltage level), and the logic 0 (lower voltage level) is used through a current limiting resistor to the individual cathode terminals of led segments.

note − common anode seven segment led displays are more popular than common cathode seven segment display because logic circuit can sink higher current as compared to they can source.

applications of seven segment led displays

seven segment led displays are widely used in the following devices −

digital watches and clocks
calculators
microwaves
remote controls
speedometers
vehicle odometers
clock radios, etc.

conclusion

seven segment displays are very commonly used in low power electronic devices like remote controls, watches, clocks, digit measuring instruments, etc. from the above discussion, we may conclude that a seven segment display consists of seven led (light emitting diode) segments that are illuminated in a pattern to display the numbers from 0 to 9. seven segment displays are also used to display some basic characters.

code converters are important components in various digital systems and devices, as they help to connect different digital devices together that support data in different formats.

in this chapter, we will highlight different types of code converters used in digital electronics, their features, and applications.

what is a code converter?

a code converter is a digital electronic circuit that is used to convert a digital code from one form to another. a digital code is nothing but a piece of data or information represented in binary format, i.e., in the form of strings of 0s and 1s.

a code converter is simply a translator which translates a code from one format to another. for example, binary to decimal converter, bcd to excess-3 converter, binary to decimal converter, etc.

code converters are essential components in various digital systems that use different encoding schemes. they help to make two different digital systems compatible with each other.

for example, consider a digital system that supports data in binary format, and we need to connect this system with another system for processing that supports data in decimal format. then, we need a data converter between them that can translate binary formatted data into decimal format for processing. this is how code converters play an important role in system interfacing.

function of a code converter

the primary function of a code converter is to accept code in one format and translate it into a different format.

a code converter reads and interprets the input code and produces an equivalent output code according to its functionality. for example, a binary-to-decimal code converter takes a binary code as input and generates an equivalent decimal code as output.

types of code converters

depending on the conversion task that a code converter performs, the following are some common types of code converters −

let us discuss each of these types of code converters −

binary to decimal converter

a type of code converter used to convert data from binary format to decimal format is called a binary-to-decimal converter.

the input to the binary-to-decimal converter is a number represented in a format of 0s and 1s. then, the converter uses an algorithm to convert the input binary number into an equivalent decimal number. finally, it generates a decimal code as output.

decimal to bcd converter

a decimal-to-bcd (binary coded decimal) converter is a type of code convert that converts a decimal number into its equivalent 4-bit binary code, called bcd code.

bcd to decimal converter

a digital circuit that can convert a binary-coded decimal (bcd) number into an equivalent decimal number is referred to as a bcd-to-decimal converter.

the input to a bcd to decimal converter is an 8421 bcd code and the output generated by the converter is a decimal number.

binary to gray code converter

a binary-to-gray code converter is a type of code converter that can translate a binary code into its equivalent gray code.

the binary-to-gray code converter accepts a binary number as input and produces a corresponding gray code as output.

gray code to binary converter

a gray code-to-binary converter is a digital circuit that can translate a gray code into an equivalent pure binary code. thus, a gray code to binary converter takes a gray code as input and gives a pure binary code as output.

bcd to excess-3 converter

a type of code converter in digital electronics that is used to convert a binary-coded decimal number into an equivalent excess-3 code is called a bcd to excess-3 converter.

excess-3 to bcd converter

an excess-3 to bcd converter is a type of code converter in digital electronics used to translate an xs-3 code into an equivalent binary-coded decimal.

therefore, an xs-3 to bcd code converter accepts a digital code in xs-3 format and produces an equivalent digital code in bcd format.

applications of code converters

in digital circuits and systems, the code converters are essential components that allow the conversion of a digital code from one format to another.

some of the important applications of code converters are listed below −

code converters are used in adc (analog-to-digital converters) and dac (digital-to-analog converters).
code converters are used in computers to translate data between different digital formats.
code converters are also employed in display devices like seven segment displays, to convert binary codes into human readable form.
in digital communication systems, the code converters are used to perform modulation and encoding tasks.
the code converters are also used as interfacing device between two digital devices or systems that use different encoding schemes.
code converters are also used in digital signal processing applications to manipulate and process signals in different formats.

code converters are integral parts of almost all digital systems and devices. they allow to interpret and process digital information in different formats.

conclusion

a code converter is nothing but a digital circuit that can convert a digital code from one format like binary to another format like decimal.

code converters are widely used in a variety of digital devices such as computers, smartphones, digital communication systems, microprocessors, microcontrollers, and more.

a type of code converter used to convert data from binary format to decimal format is called a binary-to-decimal converter.

let us now understand the logic circuit implementation of a binary-to-decimal converter.

the truth table of a two-bit binary-to-decimal converter is given below.

binary input		decimal output
b₁	b₀	decimal output
0	0	q₀
0	1	q₁
1	0	q₂
1	1	q₃

let us now derive the logical expression for each of the decimal outputs.

$$\mathrm{q_{0} \: = \: \overline{b_{1}}\: \cdot \:\overline{b_{0}}}$$

$$\mathrm{q_{1} \: = \: \overline{b_{1}}\: \cdot \: b_{0}}$$

$$\mathrm{q_{2} \: = \: b_{1} \: \cdot \:\overline{b_{0}}}$$

$$\mathrm{q_{3} \: = \: b_{1} \: \cdot \: b_{0}}$$

the logic circuit diagram of the binary-to-decimal converter is shown in the following figure.

this circuit converts a 2-bit binary number into an equivalent decimal number. however, we can implement the binary-to-decimal converter for any number of bits in the same way.

a decimal-to-bcd (binary coded decimal) converter is a type of code convert that converts a decimal number into its equivalent 4-bit binary code, called bcd code.

the truth table of the decimal to binary-coded decimal (bcd) converter is shown below.

decimal	bcd code
	b₃	b₂	b₁	b₀
0	0	0	0	0
1	0	0	0	1
2	0	0	1	0
3	0	0	1	1
4	0	1	0	0
5	0	1	0	1
6	0	1	1	0
7	0	1	1	1
8	1	0	0	0
9	1	0	0	1

the boolean expressions for converting decimal to bcd are given below −

$$\mathrm{b_{0} \: = \: d_{1} \: + \: d_{3} \: + \: d_{5} \: + \: d_{7} \: + \: d_{9}}$$

$$\mathrm{b_{1} \: = \: d_{2} \: + \: d_{3} \: + \: d_{6} \: + \: d_{7}}$$

$$\mathrm{b_{2} \: = \: d_{4} \: + \: d_{5} \: + \: d_{6} \: + \: d_{7}}$$

$$\mathrm{b_{3} \: = \: d_{8} \: + \: d_{9}}$$

the logic circuit implementation of the decimal to bcd converter is shown in the following figure.

this logic circuit can perform the conversion of a given decimal number into a binary-coded decimal or bcd code.

a digital circuit that can convert a binary-coded decimal (bcd) number into an equivalent decimal number is referred to as a bcd-to-decimal converter.

the input to a bcd to decimal converter is an 8421 bcd code and the output generated by the converter is a decimal number.

the following is the truth table of the bcd to decimal converter describing its operation.

bcd code				decimal
b₃	b₂	b₁	b₀	decimal
0	0	0	0	d₀
0	0	0	1	d₁
0	0	1	0	d₂
0	0	1	1	d₃
0	1	0	0	d₄
0	1	0	1	d₅
0	1	1	0	d₆
0	1	1	1	d₇
1	0	0	0	d₈
1	0	0	1	d₉

we can derive the boolean expressions for each of the decimal outputs in terms of 8421 bcd code. these boolean expressions are given below −

$$\mathrm{d_{0} \: = \: \overline{b_{3}} \: \overline{b_{2}} \: \overline{b_{1}} \: \overline{b_{0}}}$$

$$\mathrm{d_{1} \: = \: \overline{b_{3}} \: \overline{b_{2}} \: \overline{b_{1}} \: b_{0}}$$

$$\mathrm{d_{2} \: = \: \overline{b_{3}} \: \overline{b_{2}} \: b_{1} \: \overline{b_{0}}}$$

$$\mathrm{d_{3} \: = \: \overline{b_{3}} \: \overline{b_{2}} \: b_{1} \: b_{0}}$$

$$\mathrm{d_{4} \: = \: \overline{b_{3}} \: b_{2} \: \overline{b_{1}} \: \overline{b_{0}}}$$

$$\mathrm{d_{5} \: = \: \overline{b_{3}} \: b_{2} \: \overline{b_{1}} \: b_{0}}$$

$$\mathrm{d_{6} \: = \: \overline{b_{3}} \: b_{2} \: b_{1} \: \overline{b_{0}}}$$

$$\mathrm{d_{7} \: = \: \overline{b_{3}} \: b_{2} \: b_{1} \: b_{0}}$$

$$\mathrm{d_{8} \: = \: b_{3} \: \overline{b_{2}} \: \overline{b_{1}} \: \overline{b_{0}}}$$

$$\mathrm{d_{9} \: = \: b_{3} \: \overline{b_{2}} \: \overline{b_{1}} \: b_{0}}$$

the logic circuit implementation of the bcd to decimal converter is shown in the following figure.

a binary-to-gray code converter is a type of code converter that can translate a binary code into its equivalent gray code.

the binary-to-gray code converter accepts a binary number as input and produces a corresponding gray code as output.

here is the truth table explaining the operation of a 4-bit binary-to-gray code converter.

binary code				gray code
b₃	b₂	b₁	b₀	g₃	g₂	g₁	g₀
0	0	0	0	0	0	0	0
0	0	0	1	0	0	0	1
0	0	1	0	0	0	1	1
0	0	1	1	0	0	1	0
0	1	0	0	0	1	1	0
0	1	0	1	0	1	1	1
0	1	1	0	0	1	0	1
0	1	1	1	0	1	0	0
1	0	0	0	1	1	0	0
1	0	0	1	1	1	0	1
1	0	1	0	1	1	1	1
1	0	1	1	1	1	1	0
1	1	0	0	1	0	1	0
1	1	0	1	1	0	1	1
1	1	1	0	1	0	0	1
1	1	1	1	1	0	0	0

let us derive the boolean expressions for the gray code output bits. for this, we will simplify the truth table using the k-map technique.

k-map for gray code bit g₀

the k-map simplification to obtain the boolean expression for the gray code bit g₀ is shown in the following figure.

hence, the boolean expression for the gray code bit g₀ is,

$$\mathrm{g_{0} \: = \: \overline{b_{1}} \: b_{0} \: + \ b_{1} \: \overline{b_{0}} \: = \: b_{0} \: \oplus \: b_{1}}$$

k-map for gray code bit g₁

the k-map simplification for the gray code bit g₁ is shown below −

thus, the boolean expression for the gray code bit g₁ is,

$$\mathrm{g_{1} \: = \: \overline{b_{2}} \: b_{1} \: + \ b_{2} \: \overline{b_{1}} \: = \: b_{1} \: \oplus \: b_{2}}$$

k-map for gray code bit g₂

the k-map simplification for the gray code bit g₂ is depicted in the following figure −

the boolean expression for the gray code bit g₂ will be,

$$\mathrm{g_{2} \: = \: \overline{b_{3}} \: b_{2} \: + \ b_{3} \: \overline{b_{2}} \: = \: b_{2} \: \oplus \: b_{3}}$$

k-map for gray code bit g₃

the k-map simplification for the gray code bit g₃ is shown in the following figure −

hence, the boolean expression for the gray code bit g₃ is,

$$\mathrm{g_{3} \: = \: b_{3}}$$

let us now utilize these boolean expressions to implement the logic circuit of the binary-to-gray code converter.

the following figure shows the logic circuit diagram of a 4-bit binary code to gray code converter −

this circuit can convert a 4-bit binary number into an equivalent gray code.

we can follow the same procedure to design a binary-to-gray code converter for any number of bits.

the truth table of a 3-bit gray code to binary code converter is given below −

gray code			binary code
g₂	g₁	g₀	b₂	b₁	b₀
0	0	0	0	0	0
0	0	1	0	0	1
0	1	0	0	1	1
0	1	1	0	1	0
1	0	0	1	1	1
1	0	1	1	1	0
1	1	0	1	0	0
1	1	1	1	0	1

let us obtain the boolean expression for the binary output bits. for this, we will simplify the truth table using the k-map technique.

k-map for binary bit b₀

the k-map simplification for the binary output bit b₀ is shown in the following figure.

the boolean expression for the binary bit b₀ will be,

$$\mathrm{b_{0} \: = \: \overline{g_{2}} \: \overline{g_{1}} \: g_{0} \: + \: \overline{g_{2}} \: g_{1} \: \overline{g_{0}} \: + \: g_{2} \: \overline{g_{1}} \: \overline{g_{0}}\: + \: g_{2} \: g_{1} \: g_{0}}$$

we can further simplify this expression as follows,

$$\mathrm{\rightarrow \: b_{0} \: = \: \overline{g_{2}} \: (\overline{g_{1}} \: g_{0} \: + \: g_{1} \: \overline{g_{0}}) \: + \: g_{2} \: (\overline{g_{1}} \: \overline{g_{0}}\: + \: g_{1} \: g_{0})}$$

$$\mathrm{\rightarrow \: b_{0} \: = \: \overline{g_{2}} \: ( g_{0} \: \oplus \: g_{1}) \: + \: g_{2} \: \overline{(g_{0} \: \oplus \: g_{1})}}$$

$$\mathrm{b_{0} \: = \: g_{0} \: \oplus \: g_{1} \: \oplus \: g_{2}}$$

this is the simplified expression for the binary bit b₀.

k-map for binary bit b₁

the k-map simplification for the binary output b₁ is shown below.

the boolean expression for the binary bit b₁ is,

$$\mathrm{b_{1} \: = \: g_{2} \: \overline{g_{1}} \: + \: \overline{g_{2}} \: g_{1} \: = \: g_{1} \: \oplus \: g_{2}}$$

k-map for binary bit b₂

the following figure shows the k-map simplification for the binary bit b₂.

from this k-map, we obtain the following boolean expression −

$$\mathrm{b_{2} \: = \: g_{2}}$$

the logic circuit implementation of this 3-bit gray to binary code converter is shown in the following figure.

this logic circuit can translate a 3-bit gray code into an equivalent 3-bit binary code. we can also follow the same procedure to implement a gray code to binary code converter for any number of bits.

a type of code converter in digital electronics that is used to convert a binary-coded decimal number into an equivalent excess-3 code is called a bcd to excess-3 converter.

hence, in the case of a bcd to excess-3 code converter, the input is an 8421 bcd code and the output is an xs-3 code.

the following is the truth table of a bcd to excess-3 code converter −

bcd code				excess-3 code
b₃	b₂	b₁	b₀	x₃	x₂	x₁	x₀
0	0	0	0	0	0	1	1
0	0	0	1	0	1	0	0
0	0	1	0	0	1	0	1
0	0	1	1	0	1	1	0
0	1	0	0	0	1	1	1
0	1	0	1	1	0	0	0
0	1	1	0	1	0	0	1
0	1	1	1	1	0	1	0
1	0	0	0	1	0	1	1
1	0	0	1	1	1	0	0
1	0	1	0	x	x	x	x
1	0	1	1	x	x	x	x
1	1	0	0	x	x	x	x
1	1	0	1	x	x	x	x
1	1	1	0	x	x	x	x
1	1	1	1	x	x	x	x

let us solve the truth table using the k-map to derive the boolean expressions for the xs-3 output bits x₀, x₁, x₂, and x₃.

k-map for xs-3 bit x₀

the k-map simplification for the xs-3 bit x₀ is shown in the following figure −

on simplifying this k-map, we obtain the following boolean expression,

$$\mathrm{x_{0} \: = \: \overline{b_{0}}}$$

k-map for xs-3 bit x₁

the k-map simplification for the xs-3 bit x₁ is depicted below −

this k-map simplification gives the following boolean expression,

$$\mathrm{x_{1} \: = \: \overline{b_{1}} \: \overline{b_{0}} \: + \: b_{1} \: b_{0}}$$

k-map for xs-3 bit x₂

the k-map simplification for the xs-3 bit x₂ is shown in the figure below.

on simplifying this k-map, we obtain the following boolean expression,

$$\mathrm{x_{2} \: = \: \overline{b_{2}} \: b_{1} \: + \: \overline{b_{2}} \: b_{0} \: + \: b_{2} \: \overline{b_{1}} \: \overline{b_{0}}}$$

k-map for xs-3 bit x₃

the k-map simplification for the xs-3 bit x₃ is depicted in the figure below −

this k-map gives the following boolean expression,

$$\mathrm{x_{3} \: = \: b_{3} \: + \: b_{2} \: b_{1} \: + \: b_{2} \: b_{0}}$$

the logic circuit diagram of the bcd to xs-3 converter is shown in the following figure −

this circuit converters a 4-bit bcd code into an equivalent xs-3 code.

an excess-3 to bcd converter is a type of code converter in digital electronics used to translate an xs-3 code into an equivalent binary-coded decimal.

therefore, an xs-3 to bcd code converter accepts a digital code in xs-3 format and produces an equivalent digital code in bcd format.

the truth table of the xs-3 to bcd code converter is given below −

excess-3 code				bcd code
x₃	x₂	x₁	x₀	b₃	b₂	b₁	b₀
0	0	0	0	x	x	x	x
0	0	0	1	x	x	x	x
0	0	1	0	x	x	x	x
0	0	1	1	0	0	0	0
0	1	0	0	0	0	0	1
0	1	0	1	0	0	1	0
0	1	1	0	0	0	1	1
0	1	1	1	0	1	0	0
1	0	0	0	0	1	0	1
1	0	0	1	0	1	1	0
1	0	1	0	0	1	1	1
1	0	1	1	1	0	0	0
1	1	0	0	1	0	0	1
1	1	0	1	x	x	x	x
1	1	1	0	x	x	x	x
1	1	1	1	x	x	x	x

now, we will simplify this truth table using k-map method to obtain the boolean expression for the output bits.

k-map for bcd bit b₀

the following figure shows the k-map simplification for the bcd bit b₀.

this k-map gives the following boolean expression,

$$\mathrm{b_{0} \: = \: \overline{x_{0}}}$$

k-map for bcd bit b₁

the following figure shows the k-map simplification for the bcd bit b₁.

this k-map gives the following boolean expression,

$$\mathrm{b_{1} \: = \: \overline{x_{1}} \: x_{0} \: + \: x_{1} \: x_{0}}$$

k-map for bcd bit b₂

the k-map simplification for the bcd bit b₂ is shown below −

the simplification of this k-map gives the following boolean expression,

$$\mathrm{b_{2} \: = \: \overline{x_{2}} \: \overline{x_{1}} \: + \: \overline{x_{2}} \: \overline{x_{0}} \: + \: x_{2} \: x_{1} \: x_{0}}$$

k-map for bcd bit b₃

the k-map simplification for the bcd bit b₃ is shown in the following figure −

by simplifying this k-map, we obtain the following boolean expression,

$$\mathrm{b_{3} \: = \: x_{3} \: x_{2} \: + \: x_{3} \: x_{1} \: x_{0}}$$

we can use these boolean expressions to implement the digital logic circuit to perform the xs-3 to bcd conversion.

the logic circuit diagram to convert an xs-3 code into equivalent bcd code i.e., excess-3 to bcd converter is shown in the following figure −

this is all about some commonly used digital code converters used in various digital electronic applications.

addition is one of the most basic operations performed by different electronic devices like computers, calculators, etc. the electronic circuit that performs the addition of two or more numbers, more specifically binary numbers, is called as adder. since, the logic circuits use binary number system to perform the operations, hence the adder is referred to as binary adder

depending on the number of bits that the circuit can add, adders (or binary adders) are of two types −

half adder
full adder

in this article, we will discuss the half adder, its definition, circuit diagram, truth table, kmap, characteristic equations, and applications.

what is a half-adder?

a combinational logic circuit which is designed to add two binary digits is called as a half adder. the half adder provides the output along with a carry value (if any). the half adder circuit is designed by connecting an ex-or gate and one and gate. it has two input terminals and two output terminals for sum and carry. the block diagram and circuit diagram of a half adder are shown in figure-1.

from the logic circuit diagram of half adder, it is clear that a and b are the two input bits, s is the output sum, and c is the output carry bit.

in the case of a half adder, the output of the ex-or gate is the sum of two bits and the output of the and gate is the carry. although, the carry obtained in one addition will not be forwarded in the next addition because of this it is known as half adder.

operation of half adder

half adder adds two binary digits according to the rules of binary addition. these rules are as follows −

$$\mathrm{0 \: + \: 0 \: = \: 0}$$

$$\mathrm{0 \: + \: 1 \: = \: 1}$$

$$\mathrm{1 \: + \: 0 \: = \: 1}$$

$$\mathrm{1 \: + \: 1 \: = \: 10 \: (sum \: = \: 0 \: \& \: carry \: = \: 1)}$$

according to these rules of binary addition, we can see that the first three operations produce a sum whose length is one digit, whereas in the case of last operation (1 and 1), the sum consists of two digits. here, the msb (most significant bit) of this result is called a carry (which is 1) and the lsb (least significant bit) is called the sum (which is 0).

truth table of half adder

truth table is one that gives the relationship between inputs and outputs of a logic circuit and explains the operation of the circuit. the following is the truth table of the half-adder −

inputs		outputs
a	b	s (sum)	c (carry)
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

k-map for half adder

we can use the k-map (karnaugh map), a method for simplifying boolean algebra, to determine equations of the sum bit (s) and the output carry bit (c) of the half adder circuit.

the k-map for half adder circuit is shown in figure-2.

characteristic equations of half-adder

the characteristic equations of half adder, i.e., equations of sum (s) and carry (c) are obtained according to the rules of binary addition. these equations are given below −

the sum (s) of the half-adder is the xor of a and b. thus,

$$\mathrm{sum, \: s \: = \: a \: \oplus b \: = \: ab' \: + \: a'b }$$

the carry (c) of the half-adder is the and of a and b. therefore,

$$\mathrm{carry, \: c \: = \: a \cdot b }$$

applications of half adder

the following are some important applications of half adder −

half adder is used in alu (arithmetic logic unit) of computer processors to add binary bits.
half adder is used to realize full adder circuit.
half adder is used in calculators.
half adder is used to calculate addresses and tables.

conclusion

from the above discussion, we can conclude that half adders are one of the basic arithmetic circuits used in different electronic devices to perform addition of two binary digits. the major drawback of a half adder is that it cannot add the carry obtained from the addition of the previous stage. to overcome this drawback, full adders are used in electronic systems.

what is a full adder?

a combinational logic circuit that can add two binary digits (bits) and a carry bit, and produces a sum bit and a carry bit as output is known as a full-adder.

in other words, a combinational circuit which is designed to add three binary digits and produces two outputs (sum and carry) is known as a full adder. thus, a full adder circuit adds three binary digits, where two are the inputs and one is the carry forwarded from the previous addition. the block diagram and circuit diagram of the full adder are shown in figure-1.

hence, the circuit of the full adder consists of one ex-or gate, three and gates and one or gate, which are connected together as shown in the full adder circuit in figure-1.

operation of full adder

full adder takes three inputs namely a, b, and c_in. where, a and b are the two binary digits, and c_in is the carry bit from the previous stage of binary addition. the sum output of the full adder is obtained by xoring the bits a, b, and c_in. while the carry output bit (c_out) is obtained using and and or operations.

truth table of full adder

truth table is one that indicates the relationship between input and output variables of a logic circuit and explains the operation of the logic circuit. the following is the truth table of the full-adder circuit −

inputs			outputs
a	b	c_in	s (sum)	c_out (carry)
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

hence, from the truth table, it is clear that the sum output of the full adder is equal to 1 when only 1 input is equal to 1 or when all the inputs are equal to 1. while the carry output has a carry of 1 if two or three inputs are equal to 1.

k-map for full adder

k-map (karnaugh map) is a tool for simplifying binary complex boolean algebraic expressions. the k-map for full adder is shown in figure-2.

characteristic equations of full adder

the characteristic equations of the full adder, i.e. equations of sum (s) and carry output (c_out) are obtained according to the rules of binary addition. these equations are given below −

the sum (s) of the full-adder is the xor of a, b, and cin. therefore,

$$\mathrm{sum, \: s \: = \: a \: \oplus \: b \: \oplus \: c_{in} \: = \: a'b'c_{in} \: + \: a'bc'_{in} \: + \: ab'c'_{in} \: + \: abc_{in} }$$

the carry (c) of the half-adder is the and of a and b. therefore,

$$\mathrm{carry, \: c \: = \: ab \: + \: ac_{in} \: + \: bc_{in}}$$

advantages of full adder

the following are the important advantages of full adder over half adder −

full adder provides facility to add the carry from the previous stage.
the power consumed by the full adder is relatively less as compared to half adder.
full adder can be easily converted into a half subtractor just by adding a not gate in the circuit.
full adder produces higher output that half adder.
full adder is one of the essential part of critic digital circuits like multiplexers.
full adder performs operation at higher speed.

applications of full adder

the following are the important applications of full adder −

full adders are used in alus (arithmetic logic units) of cpus of computers.
full adders are used in calculators.
full adders also help in carrying out multiplication of binary numbers.
full adders are also used to realize critic digital circuits like multiplexers.
full adders are used to generate memory addresses.
full adders are also used in generation of program counterpoints.
full adders are also used in gpu (graphical processing unit).

conclusion

in this tutorial, we discussed all the key concepts related to full adders in digital electronics. full adders play an important role in many digital electronic circuits because a full adder can be used realize several other critical digital circuits.

in digital electronics, the binary adder is a combinational logic circuit which performs the addition of two or more binary digits. the binary addition is performed based on the boolean algebraic laws of addition, i.e.,

$$\mathrm{0 \: + \: 0 \: = \: 0}$$

$$\mathrm{0 \: + \: 1 \: = \: 1}$$

$$\mathrm{1 \: + \: 0 \: = \: 1}$$

$$\mathrm{1 \: + \: 1 \: = \: 0}$$

binary adders are classified into two types namely, serial binary adder and parallel binary adder.

in this tutorial, we will discuss serial binary adder, its definition, logic circuit diagram, and operation. so, let us start with basic introduction of serial binary adder.

what is a serial binary adder?

a serial binary adder is a binary adder circuit which is used to add binary numbers in serial form. in the serial adder, the two binary numbers which are added serially are stored in two shift registers, let shift register a and shift register b.

the logic circuit diagram of the serial binary adder is shown in figure 1.

the function of different elements of the serial adder circuit is as follows −

full adder

full adder is a digital combinational logic circuit which can add three binary digits and can produce two output bits, i.e. sum bit and carry bit. in the serial binary adder circuit, the full adder adds one pair of bits at a time.

shift register

a group of flip-flops that can store several bits of data is called a shift register. in serial binary adder, two shift registers are used, where one is for storing augend bit and the other is for storing added of the binary number.

d flip-flop

in serial adder, the d flip-flop is used to store the carry output bit. the output of this d flip-flop is used as the carry input in the next stage of addition.

operation of series binary adder

in the serial binary adder circuit, the binary digits (bits) are added one pair at a time using a full-adder circuit. the carry generated from the full adder is transferred to a d-flip flop. thus, the output of this d-flip flop is then used as the carry input for the next pair of significant bits. the sum bit s is transferred to a third shift register. now, let us understand the operation of the serial binary adder in the detail.

at beginning, the shift register a stores the augend bit of the given binary number, and the shift register b stores the addend bit. initially, the d flip flop is cleared to 0, hence no carry bit is present. the outputs of shift registers a and b supply a pair of significant bits to the full adder circuit at inputs i₀ and i₁. a shift control is used to enable the shift registers a and b and the carry flip-flop.

therefore, at each clock pulse, the registers a and b are shifted to the right, and the sum bit from output s of the full adder circuit enters the left most of the shift register a. thus, for each succeeding clock pulse a new sum bit is transferred to the shift register a and a new carry bit is transferred to the output q of the d flip flop. this process continues until the shift control is disabled.

hence, the addition of two binary numbers in serial form is accomplished by supplying a pair of bits together with the previous carry to a full adder circuit, and transferring a sum bit at a time into the shift register a.

now, we can summarize the working process of the serial binary adder as follows −

initially, the shift register a and the carry flip flop are set to 0, and the first number is added from the register b.
when the register b is shifting through the full adder, a second number is transferred to it through its serial input.
this second number is then added to the number of the register a, while a third number is transferred to into the register b through the serial input.

this process is executed repeatedly to perform the addition of two, three, or more binary number in serial form and accumulate the sum result in the shift register a.

let us stat this article with a brief introduction of binary adders and rules of binary addition. in digital electronics, an adder or binary adder is a combinational digital circuit which performs the addition of two or more binary digits. the binary addition of two bits is performed by following these four rules −

$$\mathrm{0 \: + \: 0 \: = \: 0}$$

$$\mathrm{0 \: + \: 1 \: = \: 1}$$

$$\mathrm{1 \: + \: 0 \: = \: 1}$$

$$\mathrm{1 \: + \: 1 \: = \: 10 (sum \: = \: 0; carry \: = \: 1)}$$

the first three operations produce a sum whose bit length is one binary digit. but, the sum of last combination, i.e. when augend and addend both are equal to 1, the binary sum consists of two binary digits namely, sum bit and carry bit. the most significant bit is the carry bit, while the least significant bit is the sum bit.

we also require the knowledge of full-adder circuit for better understanding of the implementation and operation of an n-bit parallel adder. the full-adder along with its block diagram and truth table is describe below.

what is full adder?

a combination digital circuit that adds two bits and a carry bit and produces a sum bit and a carry bit as output is referred to as a full adder (fa).

in other words, a binary adder circuit that can add three input bits and produces two output bits, i.e. sum bit and carry bit is called full adder. the block diagram of a full adder is shown in figure-1.

digital electronics n-bit parallel adders 1

here, a and b are the input bits, c_in is the input carry bit from previous sum, s is the output sum bit, and c_out is the output carry bit.

the operation of the full adder circuit can be understood easily from its truth table which is given below.

input			output
a	b	c_in	s	c_out
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

now, let us discuss the realization of an n-bit parallel adder using full adders.

n-bit parallel adder

parallel adder is a binary adder circuit implemented to add two binary number having n-bits (for example, to add 4-bit binary numbers, we use 4- bit parallel adder, and so on). as its name implies, the parallel adder is a digital combinational circuit that adds two binary numbers in parallel form and generates the arithmetic sum of those binary numbers in parallel form.

as we already mentioned above that a full adder can perform addition of only two one-bit binary numbers consisting of two input bits and one input carry bit, i.e. addition of three bits. but in actual practice, we have to add such binary numbers whose length is more than one bit. to add such binary numbers, we use parallel binary adder which is capable of adding the two binary numbers of any bit length such as 4-bit, 5-bit, etc.

we can implement an n-bit parallel adder with the help of full-adders connected in a chain fashion. the block diagram representation of an n-bit parallel adder using full adders is shown in figure-2.

n-bit parallel adders in digital electronics 2

from the block diagram of the n-bit parallel adder, it can be seen that the carry output from each full-adder is connected to the carry input terminal of the next higher level full-adder in the chain.

the number of full-adder to realize a parallel adder is determined from the number of bits in the two binary numbers to be added. therefore, an n-bit parallel adder requires n full-adders to perform the addition in parallel form. for example, a 2-bit parallel adder requires 2 full adders, 4-bit parallel adder consists of 4 full adders, and so on.

operation of n-bit parallel adder circuit

the working of the n-bit parallel adder shown in figure-2 can be described in the following steps −

initially, the full adder fa₁ adds two input bits a₁ and b₁ along with an input carry bit c_in, and it generates the output sum bit s₁ and the carry bit c₁ which is forwarded to the next adder (fa₂) in the chain. the sum bit s₁ is the least significant bit of the output sum.
at the next stage, the full adder circuit fa₂ becomes active and adds input bits a₂ and b₂ along with c₁. it generates the sum bit s₂ which is the second bit of the output sum, and the carry bit c₂ that is connected to the next full adder fa₃ in the chain.
this process will continue till the last full adder, i.e. fan in the chain. the full adder uses carry input c_(n-1) to add with the input bits a_n and b_n to produce the last bit of the output sum s_n and the last output carry bit c_n.

advantages of parallel adder

some important advantages of parallel adder are listed below −

the parallel adder adds bits simultaneously.
it makes addition of binary numbers fast.
parallel adder is more economical.

disadvantages of parallel adder

the major disadvantage of the parallel adder is propagation delay. since, in the parallel adder, carry from previous addition has to be propagated to the next adder which takes some time. this cause a significant propagation delay in the addition. this propagation delay is directly proportional to the number of bits in the binary numbers.

applications of parallel adder

the important applications of parallel adders are listed below −

parallel adders are used in arithmetic logic units that are used for heavy computing applications.
parallel adders are also used in parallel cellular automatic machines for parallel computing.
parallel adders are utilized for conversion of bcd into excess-1 code.
parallel adders are also used for the analysis of multiplication algorithms.

conclusion

we can conclude that the n-bit parallel adder is a combination digital circuit which is implemented using n full-adders to add two binary numbers in parallel form. the parallel adder performs addition of bits simultaneously, hence it increases the speed of binary addition.

in data processing, addition of operands is one of the most basic operations performed by different electronic devices like computers, calculators, etc. the electronic circuit that is designed to perform the addition of two or more numbers, more specifically binary numbers, is known as adder. as we know, the logic circuits use binary number system to perform the operations, hence the adder is also referred to as a binary adder.

types of adders

depending on the number of binary digits that the adder circuit can add, adders (or binary adders) are of two types −

half adder
full adder

here, we will discuss the implementation of full adder using half adder. but before that lets have a look into the basics of half adder and full adder.

what is a half adder?

half adder is a combinational logic circuit that is designed to add two binary digits. the half adder provides the output along with a carry (if any). the half adder circuit can be designed by connecting an xor gate and one and gate. it has two input terminals and two output terminals for sum (s) and carry (c). the block diagram and circuit diagram of a half adder are shown in figure-1.

in the half adder, the output of the xor gate is the sum of two bits and the output of the and gate is the carry bit. however, in the half-adder circuit, the carry obtained in one addition will not be forwarded in the next addition.

the output equation of the half adder are,

$$\mathrm{sum, \: s \: = \: a \: \oplus \: b}$$

$$\mathrm{carry, \: c \: = \: a \: \cdot \ b}$$

what is a full adder?

full adder is also a combinational logic circuit that can add two binary digits (bits) and a carry bit, and produces a sum bit and a carry bit as output.

it is clear that the logic circuit of a full adder consists of one xor gate, three and gates and one or gate, which are connected together as shown in figure-2. here, a and b are the input bits, c_in is the carry from previous addition, s is the sum bit, and c_out is the output carry bit.

the output equations of the full adder are,

$$\mathrm{sum, \: s \: = \: a \: \oplus \: b \: \oplus \: c_{in}}$$

$$\mathrm{carry, \: c_{out} \: = \: ab \: + \: ac_{in} \: + \: bc_{in}}$$

now, let us discuss the realization of the full adder using half adders

implementation of full adder using half adder

the logic diagram of the full adder using two half adders is shown in figure-3 −

logic diagram full adder using half adder

the block diagram of a full adder using two half adders is shown in figure-4.

block diagram full adder using half adder

from the logic diagram of the full adder using half adders, it is clear that we require two xor gates, two and gates and one or gate for the implementation of a full adder circuit using half-adders.

however, the implementation of full adder using half adder has a major disadvantage that is the increased propagation delay. that means, the input bits must propagate through several gates in succession that increases the total propagation delay of the full adder circuit.

an adder circuit is one of the important digital circuits used in computers, calculators, digital processing units, etc. there are two types adder circuits named half-adder and full-adder. both the half adder and the full adder circuits are used to perform addition and also widely used for performing various arithmetic functions in the digital circuits.

what is a half adder?

a combinational logic circuit which is designed to add two binary digits is known as half adder. the half adder provides the output along with a carry value (if any). the half adder circuit is designed by connecting an ex-or gate and one and gate. it has two input terminals and two output terminals for sum and carry.

difference between half adder and full adder 1

in case of half adder, the output of the ex-or gate is the sum of two bits while the output of the and gate is the carry. however, the carry obtained is one addition will not be forwarded in the next addition, so it is called half adder.

the output equations of the half adder are −

$$\mathrm{sum, \: s \: = \: a \oplus{b}}$$

$$\mathrm{carry, \: c \: = \: a\cdot b}$$

what is a full adder?

a combinational circuit which is designed to add three binary digits and produce two outputs is known as full adder. the full adder circuit adds three binary digits, where two are the inputs and one is the carry forwarded from the previous addition.

difference between half adder and full adder 2

the circuit of the full adder consists of two ex-or gates, two and gates and one or gate, which are connected together as shown in the full adder circuit.

the output equations of the full adder are −

$$\mathrm{sum, \: s \: = \: a \oplus{b} \oplus{c_{in}}}$$

$$\mathrm{carry, \: c \: = \: ab \: + \: bc_{in} \: + \: ac_{in}}$$

difference between half adder and full adder

the following table shows the main differences between half adder and full adder circuit.

parameter	half adder	full adder
definition	half adder is a combinational digital circuit which can add two 1-bit binary numbers.	full adder is a combinational digital circuit which can add three single-bit binary number, where two are the inputs and the third is the carry forwarded from the previous output.
circuit components	the circuit of the half adder consists of one ex-or gate and one and gate.	the circuit of full adder consists of two ex-or gates, two and gates and one or gate.
addition of carry bit	the half adder does not add the carry generated in the previous addition to the next addition.	in case of full adder, the carry produced in the previous addition is added in the next addition.
number of input and output terminals	half adder circuit has two input terminals viz. a and b and two output terminals, viz. sum and carry.	full adder circuit has three input terminals viz. a, b and cin and two output terminals, i.e., sum and carry.
logical expressions	for half adder circuit, the logical expressions of the outputs are − $\mathrm{s \: = \: a \oplus{b}}$ $\mathrm{c \: = \: a\cdot b} $	for full adder circuit, the logical expressions of the outputs are − $\mathrm{s \: = \: a \oplus{b} \oplus{c_{in}}}$ $\mathrm{c \: = \: ab \: + \: bc_{in} \: + \: ac_{in}}$
substitution	a half adder circuit cannot be used as a full adder circuit.	a full adder circuit can substitute a half adder circuit.
design	the circuit of a half adder is simple and easy to implement.	the circuit of a full adder has relatively complex design.
alternate name	for half adder, there is no alternate name.	full adder is also called ripple-carry adder.
applications	half adder circuits are used in computers, calculators, and various digital measuring instruments.	full adders are mainly used for multiple bit addition, in digital processing devices, etc.

conclusion

from the above discussion, it is clear that there are several differences between a half-adder circuit and a full-adder circuit. however, both half adder and full adder circuits are the basic building blocks of many digital circuits that are used to perform arithmetic operations such as calculators, computers, digital measuring devices, digital processors, etc.

one of the main advantage of using half adders and full adders in the digital circuits is that they are designed by using logic gates that process the input data very fast. the typical processing speed of the logic gates is of the order of μs (microseconds). hence, for performing arithmetic operations at high speed, we use half adder and full adder circuits.

a binary adder-subtractor is a digital circuit that is used to perform two basic arithmetic operations namely, binary addition and binary subtraction. it is an important component in various digital systems like computers, calculators, etc.

the most significant advantage of using a binary adder-subtractor is that it combines the addition and subtraction operations in a single circuit which results in compact size and lower cost.

read this chapter to understand the circuit and operation of a binary adder-subtractor.

what is a binary adder-subtractor?

in digital electronics, there is a digital circuit which employed for performing addition and subtraction operations, it is called a binary adder-subtractor.

a binary adder-subtractor is a specially designed digital arithmetic circuit that combines the functionality of addition and subtraction of binary numbers in a single circuit.

a binary adder-subtractor circuit performs the binary addition and subtraction operations on two binary numbers by following the rules given below.

rules of binary addition

the following rules are to be followed while performing binary addition −

first bit (a)	second bit (b)	sum (a + b)	carry
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

rules of binary subtraction

the following table shows the rules to be followed while performing binary subtraction −

first bit (a)	second bit (b)	sum (a - b)	borrow
0	0	0	0
0	1	1	1
1	0	1	0
1	1	0	0

this is all about a basic introduction to binary adder-subtractor and the rules of binary addition and subtraction. let us now understand the circuit construction of binary adder-subtractor.

binary adder-subtractor circuit

the logic circuit of a binary adder-subtractor consists of several full-adder circuits connected together. it also consists of a control circuit consisting of xor gates and performs the mode selection function i.e., the control circuit is used to switch the circuit operation between addition and subtraction.

the circuit diagram of a binary adder-subtractor which can perform the addition or subtraction of two 4-bit binary numbers (say a and b) is shown below −

components of a binary adder-subtractor

the circuit of a binary adder-subtractor consists of the following main components −

full adders

a full adder is a binary arithmetic circuit used to perform the addition of three binary bits at a time. it produces two outputs namely a sum and a carry. in a binary adder-subtractor circuit, the full adder circuit can also perform the subtraction operation using the complement mechanism.

control circuit

it is a logic circuit used for mode selection i.e., addition mode or subtraction mode. the control circuit of a binary adder-subtractor is designed using xor gates.

working of binary adder-subtractor

let us now understand the operation of a binary adder-subtractor circuit shown in the above figure.

the circuit shown in the above figure is a 4-bit binary adder-subtractor. therefore, it can perform addition or subtraction of two 4-bit binary numbers, say a and b.

in this circuit, the input m is called the mode input. it controls the operation of the circuit as described below −

when m = 0, the circuit operates as a binary adder. under this mode, we get $\mathrm{b_{x} \: \oplus \: 0 \: = \: b_{x}}$. thus, each full adder receives the inputs a_x and b_x and performs their addition, i.e., a_x + b_x.
when m = 1, the circuit operates as a binary subtractor. in this case, we get $\mathrm{b_{x} \: \oplus \: 1 \: = \: b_{x}}$ and the input carry c_in = 1. under this mode, the full adders receive b_x inputs in their complemented form and a 1 is added through the input carry c_in. hence, the final output of the circuit is a_x + 2s complement of b_x which is the subtraction of a_x and b_x.

this is how the binary adder-subtractor circuit performs both binary addition and binary subtraction operations.

we can conclude the working of a binary adder-subtractor in the following points −

first of all, select the mode of operation (addition or subtraction) of the circuit. to perform binary addition, set m = 0, and to perform binary subtraction, set m = 1.
supply the two input binary numbers to be added or subtracted.
the circuit will perform the addition or subtraction of input numbers depending on the selected mode and produce a result (either a sum or a difference).

advantages of binary adder-subtractor

in the field of digital circuit design, it is important to make the circuit compact as much as possible. since a binary adder-subtractor circuit combines both binary addition and subtraction operations in a single circuit. it results in the following key advantages −

reduced circuit complexity
compact and simpler system design
versatility
ability to perform fast and efficient arithmetic operations
reduced need for hardware components
compatibility with a wide range of digital systems and devices
low power consumption, etc.

limitations of binary adder-subtractor

binary adder-subtractor has several advantages as listed above. but it also has some disadvantages and limitations.

some of the key limitations of binary adder-subtractor are listed below −

a binary adder-subtractor requires more advanced circuit components and algorithms to achieve high precision and accuracy in addition and subtraction operations.
the functionality of a binary adder-subtractor is limited to addition and subtraction operations only. it requires additional circuitry and algorithms to implement other mathematical operations like multiplication and division.
the circuit complexity of a binary adder-subtractor is increased significantly when it is designed to perform addition and subtraction of large numbers of bits and floating-point numbers.
when the number of digits increases in the numbers to be added or subtracted, the circuit becomes slower due to propagation delay.
a binary adder-subtractor has a limited dynamic range due to which overflow or underflow conditions can occur when dealing with very large or very small numbers respectively.
since a binary adder-subtractor uses 2s complement arithmetic to perform binary subtraction. to implement this operation, we require an additional logic circuit which increases the overall complexity of the circuit.

while designing a binary adder-subtractor, we have to take care of all these limitations to ensure higher efficiency and better performance of the circuit.

applications of binary adder-subtractor

in digital electronics, the binary adder-subtractor finds applications in a variety of digital systems and electronic devices. some common devices are listed below in which the binary adder-subtractor is used as a crucial component −

arithmetic logic units − to perform arithmetic and logical operations.
microprocessors and microcontrollers − to perform mathematical computations.
communication systems − to process digital signals and filter operations on binary data.
calculators − to perform addition and subtraction operations.
control systems − to perform real-time signal processing and produce feedback and other control signals.

conclusion

in this chapter, we explained the basic theory and working of binary adder-subtractor. a binary adder-subtractor is a digital electronic circuit that can perform both addition and subtraction of binary numbers. it combines two arithmetic operations (addition and subtraction) into a single circuit and hence reduces the circuit complexity and size of the digital system.

binary adder-subtractor are widely used in various digital systems and devices such as microprocessors, microcontrollers, calculators, and more.

in digital electronics, a subtractor is a combinational logic circuit that can perform the subtraction of two number (binary numbers) and produce the difference between them. it is a combinational circuit that means its output depends on its present inputs only. although, in practice, the subtraction of two binary number is accomplished by taking the 1's or 2's compliment of the subtrahend and adding it to the minuend.

in this way, the subtraction operation of binary numbers can be converted into simple addition operation which makes hardware construction simple and less expensive. there are two types of subtractors namely, half subtractor and full subtractor.

in this article, we will discuss the half subtractor, its basic definition, circuit diagram, truth table, characteristic equation, etc. so let's begin with the basic definition of half subtractor.

what is a half-subtractor?

a half-subtractor is a combinational logic circuit that have two inputs and two outputs (i.e. difference and borrow). the half subtractor produces the difference between the two binary bits at the input and also produces a borrow output (if any). in the subtraction (a-b), a is called as minuend bit and b is called as subtrahend bit. the block diagram and logic circuit diagram of the half subtractor is shown in figure-1.

hence, from the logic circuit diagram, it is clear that a half subtractor can be realized using an xor gate together with a not gate and an and gate.

in the half subtractor as shown in figure-1, a and b are the inputs, d and b are the outputs. where, d indicates the difference and b indicates the borrow output. the borrow output (b) is the signal that tells the next stage that a 1 has been borrowed.

operation of half subtractor

now, let us understand the operation of the half subtractor circuit. half subtractor performs its operation to find the difference of two binary digits according to the rules of binary subtraction, which are as follows −

the output borrow of b is zero (0) as long as the minuend bit (a) is greater than or equal to the subtrahend bit (b), i.e. a b. the output borrow is a 1 when a = 0 and b = 1.

from the logic circuit diagram of the half subtractor, it is clear that the difference bit (d) is obtained by the xor operation of the two inputs a and b, and the borrow bit is obtained by and operation of the compliment of the minuend (a') with the subtrahend (b).

truth table of half subtractor

the following is the truth table the half-subtractor −

inputs		outputs
a	b	d (difference)	b (borrow)
0	0	0	0
0	1	1	1
1	0	1	0
1	1	0	0

k-map for half subtractor

we can use the k-map (or karnaugh map), a method for simplifying boolean algebra, to determine equations of the difference bit (d) and the output borrow (b).

the k-map simplification for half subtractor is shown in figure-2.

characteristic equation of half subtractor

the characteristic equations of the half subtractor, i.e. equations of the difference bit (d) and the output borrow bit (b) are obtained by following the rules of binary subtraction. these equations are given as follows −

the difference bit (d) of the half subtractor is given by xoring the two inputs a and b. therefore,

$$\mathrm{difference, \: d \: = \: a \oplus b \: = \: a'b \: + \: ab'}$$

the borrow (b) of the half subtractor is the and of a (compliment of a) and b. therefore,

$$\mathrm{borrow, \: b \: = \: a'b}$$

applications of half subtractor

the following are some important applications of half subtractor −

half subtractor is used in alu (arithmetic logic unit) of processors.
half subtractor can also be used in amplifiers to compensate the sound distortion.
it is also used to decrease the force of radio signals or audio signals.
half subtractor is also used to increase or decrease operators.

conclusion

from the above discussion, we can conclude that a half subtractor is a combinational logic circuit that can calculate the difference of two binary digits. a half subtractor can only be used to subtract the lsb (least significant bit) of the subtrahend from the lsb of the minuend when one binary number is subtracted from another binary number.

what is a full-subtractor?

a full-subtractor is a combinational circuit that has three inputs a, b, bin and two outputs d and b. where, a is the minuend, b is subtrahend, b_in is borrow produced by the previous stage, d is the difference output and b is the borrow output.

as we know that the half-subtractor can only be used for subtraction of lsb (least significant bit) of binary numbers. if there is any borrow during the subtraction of the lsbs of two binary numbers, then it will affect the subtraction of next stages. therefore, the subtraction with borrow are performed by a full subtractor.

the block diagram and circuit diagram of a full-subtractor is shown in figure-1.

therefore, we can realize the full-subtractor using two xor gates, two not gates, two and gates, and one or gate.

operation of full subtractor

now, let us understand the operation of the full subtractor. full subtractor performs its operation to find the difference of two binary numbers according to the rules of binary subtraction, which are as follows −

in the case of full subtractor, the 1s and 0s for the output variables (difference and borrow) are determined from the subtraction of a b b_in.

from the logic circuit diagram of the full subtractor, it is clear that the difference bit (d) is obtained by the xor operation of the two inputs a, b, and b_in, and the output borrow bit (b) is obtained by not, and, and or operations of variable a, b, and b_in.

truth table of full-subtractor

the truth table is one that gives relationship between input and output of a logic circuit. the following is the truth table of the full-subtractor −

inputs			outputs
a	b	b_in	d (difference)	b (borrow)
0	0	0	0	0
0	0	1	1	1
0	1	0	1	1
0	1	1	0	1
1	0	0	1	0
1	0	1	0	0
1	1	0	0	0
1	1	1	1	1

k-map for full subtractor

we can use the k-map (or karnaugh map), a method for simplifying boolean algebra, to determine equations of the difference bit (d) and the output borrow bit (b).

the k-map simplification for half subtractor is shown in figure-2.

characteristic equations of full subtractor

the characteristic equations of the full subtractor, i.e. equations of the difference (d) and borrow output (b) are obtained by following the rules of binary subtraction. these equations are given below −

the difference (d) of the full subtractor is the xor of a, b, and b_in. therefore,

$$\mathrm{difference, \: d \: = \: a \oplus b \oplus b_{in} \: = \: a'b'b_{in} \: + \: ab'b'_{in} \: + \: a'bb'_{in} \: + \: abb_{in}}$$

the borrow (b) of the full subtractor is given by,

from the logic circuit diagram and k-map −

$$\mathrm{borrow, \: b \: = \: a'b \: + \: \left ( a \oplus b \right ) \: 'b_{in}}$$

from truth table

$$\mathrm{borrow, \: b \: = \: a'b'b_{in} \: + \: a'bb'_{in} \: + \: a'bb_{in} \: + \: abb_{in}}$$

$$\mathrm{borrow, \: b \: = \: a'b \left ( b_{in} \: + \: b'_{in} \right ) \: + \: \left (ab \: + \: a'b' \right )b_{in} \: = \: a'b \: + \: \left (a \oplus b \right )'b_{in}}$$

applications of full subtractor

the following are some important applications of full subtractor −

full subtractors are used in alu (arithmetic logic unit) in computers cpus.
full subtractors are extensively used to perform arithmetical operations like subtraction in electronic calculators and many other digital devices.
full subtractors are used in different microcontrollers for arithmetic subtraction.
they are used in timers and program counters (pc).
full subtractors are also used in processors to compute addresses, tables, etc.
full subtractors are also used in dsp (digital signal processing) and networking based systems.

conclusion

from the above discussion, we can conclude that a full-subtractor is a combinational logic circuit that can compute the difference of three binary digits. in a full subtractor, the borrow (if any) from the previous stage is also used in subtraction operation in the next stages. therefore, full subtractors are used to perform subtraction of binary numbers having any number of digits.

in digital electronics, adder and subtractor are the two most basic arithmetic combinational circuits. the adder is a combinational arithmetic circuit used to perform addition of two or more binary numbers. whereas, the subtractor is a combination arithmetic circuit used to perform subtraction of two binary numbers.

depending on the form in which the addition and subtraction of binary numbers are executed, the adder and subtractor are classified into following types −

serial adder
parallel adder
serial subtractor
parallel subtractor

this tutorial is meant for explaining parallel adder and parallel subtractor. but before that let us first discuss the rules of boolean algebra followed to perform the binary addition and subtraction.

binary addition

the following rules are followed while performing binary addition −

binary digit a	binary digit b	sum (a + b)	carry
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

binary subtraction

the following rules are to be followed while performing binary subtraction −

binary digit a	binary digit b	difference (a - b)	borrow
0	0	0	0
0	1	1	1
1	0	1	0
1	1	0	0

now, let us discuss the parallel adder and parallel subtractor in detail.

what is parallel adder?

a digital circuit that adds two binary numbers of any bit length in parallel form and produces the sum of those number in parallel form is called a parallel adder.

a parallel adder basically consists of full adders in a chain form as shown in figure 1. here, the output bit of each full adder is connected to the input carry terminal of the next full adder circuit in the chain.

the parallel adder shown in figure 1 is a 4-bit parallel adder as it can add two binary number of 4 bits. although, we can design a parallel adder circuit for any number of bits by increasing the number of full adders in the chain.

in the above parallel adder circuit, the bit a is representing the augend bits and b is representing the addend bits. the first input carry bit to the parallel adder is c_in and the output carry bit of the parallel adder is c₄. the output sum bits are designated by s. we can also construct a parallel adder in the form of an ic. for example, when the 4-bit parallel adder is formed in the ic form, then it will have four terminals for augend bits, 4 terminals for addend bits, 4 terminals for sum bits, and 2 terminals for input and output carry bits.

working of parallel adder

the parallel adder shown in figure-1 performs the binary addition of two numbers as per the following step −

step 1 − firstly, the full adder circuit fa₁ adds the bits a₁ and b₁ along with the input carry bit cin to produce the sum bit s₁, where it is the lsb (least significant bit) of the output sum. at this stage, a carry bit c₁ is generated which is transferred to the next full adder circuit in the chain.

step 2 − the full adder circuit fa₂ adds bits a₂ and b₂ along with the carry bit c₁ from the previous addition. it produces the sum bit s₂ which is the second bit of the output sum, and a carry bit c₂ is also produced which again forwarded to the next full adder fa₃.

step 3 − the full adder circuit fa₃ adds inputs bits a₃ and b₃ along with the carry bit c₂ from previous addition to produce sum bit s₃ and carry bit c₃.

step 4 − the full adder fa₄ adds input bits a₄ and b₄ along with the carry bit c₃ forward from fa₃. it generates the last sum bit s₄ and a last carry bit c₄.

step 5 − the output sum of the parallel adder is then given by,

$$\mathrm{s_{out} \: = \: c_{4} \: s_{4} \: s_{3} \: s_{2} \: s_{1}}$$

what is parallel subtractor?

a digital arithmetic circuit which is used to find the arithmetic difference of two binary numbers in parallel form is called a parallel subtractor.

we can implement a parallel subtractor in several ways such as combining half subtractors and full subtractors, all full subtractors, all full adders, etc. here, we have realized a 4-bit parallel subtractor using all full adders with subtrahend bit complemented as shown in figure 2.

this is the 4-bit parallel subtractor, however, we can implement a parallel subtractor by adding any number of full adders in the chain of the circuit shown in figure-2.

the binary subtraction of two binary numbers can be conveniently accomplished by means of 1's or 2's complement. where, the complement method converts the subtraction operation in simple addition operation.

the 2's complement of binary numbers is obtained by taking the 1's complement and adding 1 to the least significant pair of bits. the 1's complement can be implemented with the help of a not gate (inverter).

working of parallel subtractor

the parallel subtractor shown in above figure-2 carries out the subtraction of two binary numbers as per the following steps −

step 1 − firstly, the 1's complement of bit b₁ obtained using an inverter and a 1 (c_in) are added to obtain the 2's complement of the bit b₁. then, this 2's complemented b₁ is further added to a₁. this will produce first bit of the output difference designated by s₁, and a carry bit c₁ which is connected to the input carry of the fa₂.

step 2 − the full adder fa₂ uses the input carry bit c₁ to add with its input bit a₂ and the 2's complement of the input bit b₂ to produce the second difference bit (s₂) and the carry bit c₂.

step 3 − the full adder fa₃ uses the input carry bit c₂ to add with its input bit a₃ and the 2's complement of the input bit b₃ to produce the third difference bit (s₃) and the carry bit c₃.

step 4 − finally, the full adder fa₄ uses the carry bit c₃ to add with its input bit a₄ and the 2's complement of the input bit b₄ to produce the last difference bit (s₄) and last carry bit c₄.

once all the result bits are produced, they are expressed to give the difference of the two binary numbers as s₄s₃s₂s₁ and borrow bit c₄.

conclusion

this is all about parallel adder and parallel subtractor in digital electronics. the most significant advantage of the parallel adder and subtractor is that they perform the arithmetic addition and subtraction of two binary numbers faster as compared to the serial adder and subtractor.

a subtractor is a combinational logic circuit that can perform the subtraction of two numbers (or binary numbers) and produce the difference between them. it is a combinational logic circuit. therefore, the output of the subtractor depends only on its present inputs.

there are two types of subtractors namely,

half subtractor
full subtractor

read this tutorial to find out how you can realize a full subtractor using half subtractors. for the implementation of a full subtractor, we require two half subtractors. let's start with a brief overview of half and full subtractors.

what is a half subtractor?

a half-subtractor is a combinational logic circuit that has two inputs and two outputs where one output is difference bit (d) and another is the borrow bit (b). the half subtractor produces the difference between the two binary bits and also produces a borrow output (if any). in the subtraction (a-b), a is called minuend and b is called subtrahend bit.

the block diagram and logic circuit diagram of the half subtractor are shown in figure-1.

from the logic diagram of the half subtractor, it can be seen that a half subtractor can be realized using an xor gate together with a not gate and an and gate.

the difference bit (d) of the half subtractor is given by xoring the two inputs a and b. therefore,

$$\mathbf{difference,\: d \: = \: a \oplus b \: = \: a'b \: + \: ab'}$$

the borrow (b) of the half subtractor is the and of a' (compliment of a) and b. therefore,

$$\mathbf{borrow, \: b \: = \: a'b}$$

what is a full subtractor?

a full subtractor is also a combinational logic circuit which has three inputs a, b, bin and two outputs "d" and "b". where, "a" is the minuend bit, "b" is the subtrahend bit, "bin" is borrow produced at the previous stage, d is the output difference bit and b is the output borrow bit.

the block diagram and circuit diagram of a full-subtractor is shown in figure-2.

from the logic diagram of the full subtractor, we can see that the implementation of a fullsubtractor requires two xor gates, two not gates, two and gates, and one or gate.

now, let us discuss the realization of full subtractor using two half subtractors.

implementation of a full subtractor using two half subtractors

a full subtractor can be realized using two half subtractors. it will take two half-subtractors and one or gate. the logic circuit diagram of the full subtractor using two half subtractors is shown in figure-3.

the first half subtractor performs xor operation on input bits a and b, and and operation on a' and b to produce an intermediate borrow bit

the second half subtractor performs the xor operation on the output of first xor gate and the input borrow bit (b_in), and the and gate of the second half circuit gives an output equal to (a'b + ab')'.b_in.

the output of the second xor gate is the output different bit (d), and the output borrow bit (b) is obtained by oring the outputs of two and gates.

in this way, we can realize a full subtractor by cascading two half subtractors, as shown in the above figure

in digital electronics, a subtractor is a combinational logic circuit that performs the subtraction of two binary numbers. however, the subtraction of binary number can be performed using adder circuits by taking 1s or 2s compliments. but, we may also realize a dedicate circuit to perform the subtraction of two binary numbers.

in the subtraction of two binary numbers, each subtrahend bit of the number is subtracted from its corresponding significant minuend bit to form a difference bit. during the subtraction, if the minuend bit is smaller than the subtrahend bit, then a 1 is borrowed from the next position. depending upon the number of bits taken as input, there are two types of subtractors namely, half subtractor and full subtractor.

a half subtractor is one which takes two binary digits as input and gives a difference bit and a borrow bit (if any) as output.

on the other hand, a full subtractor is one that takes three bits as input, i.e. two are the input bits and one is the input borrow bit from the previous stage, and gives a difference bit and a output borrow bit as the output.

since a subtractor is a combinational logic circuit, i.e. it is made of logic gates. we can realize a full adder circuit using different types of logic gates like and, or, not, nand, nor, etc.

here, we will discuss the implementation of a half subtractor using nand gates. but before that lets have a look into the basics of the half subtractor.

what is half subtractor?

a half-subtractor is a combinational circuit which has two inputs and two outputs where one output is difference and another is borrow bit. the half subtractor produces the difference between the two binary bits at the input and also produces a borrow output (if any). in the subtraction (a-b), a is called as minuend bit and b is called as subtrahend bit. the block diagram of the half subtractor is shown in figure-1.

here, a and b are the input variables (binary digits) and d is the output difference bit and b is the borrow bit. we can understand the operation of a half subtractor with the help of its truth table.

truth table of half subtractor

the following is the truth table the half subtractor −

inputs		outputs
a	b	d (difference)	b (borrow)
0	0	0	0
0	1	1	1
1	0	1	0
1	1	0	0

using this truth table, we can determine the output equation of the half subtractor. the following are the equations of difference bit (d) and borrow bit (b) −

different bit (d) −

$$\mathrm{difference, \: d \: = \: a'b \: + \: ab' \: = \: a \oplus b}$$

borrow bit (b)

$$\mathrm{borrow, \: b \: = \: a'b}$$

now, let us discuss the realization of half subtractor using nand gates.

half subtractor using nand gates

we may implement the logic circuit of half subtractor using nand gates only as shown in figure-2.

from this logic circuit diagram, we can see that 9 nand gates are required for realization of the half subtractor.

the output equations of the half subtractor in nand logic are as follows −

difference bit (d)

$$\mathrm{difference, \: d \: = \: \overline{\overline{a \cdot \: \overline{ab}} \: \cdot \: \overline{b \cdot \overline{ab}}} \ = \: a \oplus b}$$

borrow bit (b)

$$\mathrm{borrow, \: b \: = \: \overline{\overline{b \cdot \: \overline{ab}}} \: = \: \overline{a} \: b}$$

in this way, we can realize the half subtractor using the nand gates only.

digital circuits are classified into two major categories namely, combinational circuits and sequential circuits. we have already discussed about combinational circuits in the earlier chapters of this tutorial. this chapter will highlight the details of sequential circuits.

a sequential circuit is a type of digital logic circuit whose output depends on present inputs as well as past operation of the circuit. let us start this section of the tutorial with a basic introduction to sequential circuits.

what is a sequential circuit?

a sequential circuit is a logic circuit that consists of a memory element to store history of past operation of the circuit. therefore, the output of a sequential circuit depends on present inputs as well as past outputs of the circuit.

the block diagram of a typical sequential circuit is shown in the following figure −

here, it can be seen that a sequential circuit is basically a combination of a combinational circuit and a memory element. the combinational circuit performs the logical operations specified, while the memory element records the history of operation of the circuit. this history is then used to perform various logical operations in future.

the sequential circuits are named so because they use a series of latest and previous inputs to determine the new output.

main components of sequential circuit

a sequential circuit consists of several different digital components to process and hold information in the system. here are some key components of a sequential circuit explained −

logic gates

the logic gates like and, or, not, etc. are used to implement the data processing mechanism of the sequential circuits. these logic gates are basically interconnected in a specific manner to implement combinational circuits to perform logical operations on input data.

memory element

in sequential circuits, the memory element is another crucial component that holds history of circuit operation. generally, flip-flops are used as the memory element in sequential circuits.

in sequential circuits, a feedback path is provided between the output and the input that transfers information from output end to the memory element and from memory element to the input end.

all these components are interconnected together to design a sequential circuit that can perform complex operations and store state information in the memory element.

types of sequential circuits

based on structure, operation, and applications, the sequential circuits are classified into the following two types −

asynchronous sequential circuit
synchronous sequential circuit

let us discuss both of these sequential circuits in detail.

asynchrnous sequential circuit

a type of sequential circuit whose operation does not depend on the clock signals is known as an asynchronous sequential circuit. this type of sequential circuits operates using the input pulses that means their state changes with the change in the input pulses.

the main components of the asynchronous sequential circuits include un-clocked flip flops and combinational logic circuits. the block diagram of a typical asynchronous sequential circuit is shown in the following figure.

from this diagram, it is clear that an asynchronous sequential circuit is similar to a combinational logic circuit with a feedback mechanism.

asynchronous sequential circuits are mainly used in applications where the clock signals are not available or practical to use. for example, in conditions when speed of the task execution is important.

asynchronous sequential circuits are relatively difficult to design and sometimes they produce uncertain output.

the ripple counter is a common example of asynchronous sequential circuit.

synchronous sequential circuit

a synchronous sequential circuit is a type of sequential circuit in which all the memory elements are synchronized by a common clock signal. hence, synchronous sequential circuits take a clock signal along with input signals.

in synchronous sequential circuits, the duration of the output pulse is equivalent to the duration of the clock pulse applied. take a look at the block diagram of a typical synchronous sequential circuit −

in this figure, it can be seen that the memory element of the sequential circuit is synchronized by a clock signal.

the major disadvantage of the synchronous sequential circuits is that their operation is quite slow. this is because, every time the circuit has to wait for a clock pulse for the operation to take place. however, the most significant advantage of synchronous sequential circuits is that they have a reliable and predictable operation.

some common examples of synchronous sequential circuits include counters, registers, memory units, control units, etc.

sequential circuits vs. combinational circuits

given below is a list of some of the main advantages of using sequential circuits over combinational logic circuits −

sequential circuits can retain the operation history which is important in various applications like data storage, feedback control systems, etc.
sequential circuits exhibit dynamic behavior and can execute complex operation in real time.
sequential circuits comprise a feedback mechanism which improves the stability and optimizes the system performance.
synchronous sequential circuits use a common clock signal for synchronization that ensures reliable operation of the circuit.
sequential circuits can perform more complex operations using simpler circuit designs than combinational circuits. hence, their hardware complexity is lesser.

disadvantages of sequential circuits

sequential circuits do have several disadvantages too. some of the key disadvantages of using sequential circuits are listed below −

sequential circuits have higher propagation delay because the input signal passes through multiple stages of logic circuits and memory elements.
sequential circuits are relatively complicated and time taking process to design and analyze.
sequential circuits require a proper synchronization and clock distribution to work as intended.
as compared to combinational circuits, sequential circuits consume relatively more power due to complex design and use of additional components like clock and memory element.

applications of sequential circuits

sequential circuits are used in a wide range of applications in the field of digital electronics.the following are some common examples of applications of sequential circuits −

sequential circuits are used in digital counters employed in applications like frequency division, event counting, time keeping, and more.
sequential circuits are also used in digital memory devices like flip-flops, registers, etc. to store and retrieve data.
sequential circuits are used to design control circuits in digital systems.
sequential circuits play an important role in sequential logic and state-based data processing operations.
sequential circuits are also used in automation systems to control the operation of machines based on predefined logics.
in communication systems, sequential circuits are used to implement communication protocols and data transmission standards.

conclusion

sequential circuits are important components in digital electronic systems. a sequential circuit is nothing but a combination of combinational logic circuit and a memory element, where the memory element is connected in a feedback mechanism with the combinational circuit.

the most important thing to be noted about sequential circuits is that their output is determined by both present inputs and previous inputs and outputs.

sequential circuits are used to design complex digital systems that can perform advance operations like real-time data processing, storage and transmission of data, counting events, and more.

in this chapter, let us discuss about the clock signal and types of triggering one by one.

clock signal

clock signal is a periodic signal and its on time and off time need not be the same. we can represent the clock signal as a square wave, when both its on time and off time are same. this clock signal is shown in the following figure.

in the above figure, square wave is considered as clock signal. this signal stays at logic high (5v) for some time and stays at logic low (0v) for equal amount of time. this pattern repeats with some time period. in this case, the time period will be equal to either twice of on time or twice of off time.

we can represent the clock signal as train of pulses, when on time and off time are not same. this clock signal is shown in the following figure.

in the above figure, train of pulses is considered as clock signal. this signal stays at logic high (5v) for some time and stays at logic low (0v) for some other time. this pattern repeats with some time period. in this case, the time period will be equal to sum of on time and off time.

the reciprocal of the time period of clock signal is known as the frequency of the clock signal. all sequential circuits are operated with clock signal. so, the frequency at which the sequential circuits can be operated accordingly the clock signal frequency has to be chosen.

types of triggering

following are the two possible types of triggering that are used in sequential circuits.

level triggering
edge triggering

level triggering

there are two levels, namely logic high and logic low in clock signal. following are the two types of level triggering.

positive level triggering
negative level triggering

if the sequential circuit is operated with the clock signal when it is in logic high, then that type of triggering is known as positive level triggering. it is highlighted in below figure.

if the sequential circuit is operated with the clock signal when it is in logic low, then that type of triggering is known as negative level triggering. it is highlighted in the following figure.

edge triggering

there are two types of transitions that occur in clock signal. that means, the clock signal transitions either from logic low to logic high or logic high to logic low.

following are the two types of edge triggering based on the transitions of clock signal.

positive edge triggering
negative edge triggering

positive edge triggering

if the sequential circuit is operated with the clock signal that is transitioning from logic low to logic high, then that type of triggering is known as positive edge triggering. it is also called as rising edge triggering. it is shown in the following figure.

negative edge triggering

if the sequential circuit is operated with the clock signal that is transitioning from logic high to logic low, then that type of triggering is known as negative edge triggering. it is also called as falling edge triggering. it is shown in the following figure.

in the coming chapters, we will discuss about various sequential circuits based on the type of triggering that can be used in it.

a latch is an asynchronous sequential circuit whose output changes immediately with the change in the applied input. a latch is used to store 1 bit information in a digital system, so it is considered as the most elementary memory element.

in this chapter, we will explain in detail about latches in digital electronics along with their types and applications.

what is a latch?

in digital electronics, a latch is an asynchronous sequential circuit that can store 1-bit information. it is used as the fundamental memory element in digital circuits.

a latch can have two stable states namely, set and reset. the set state is denoted by the logic 1 and the reset state is represented by the logic 0. due to these two stable states, a latch is also known as a bistable-multivibrator. the state of a latch toggles according to the applied input.

the most important thing to be noted about latches is that they do not have a clock signal for synchronization. that is why they are called asynchronous sequential circuits.

the logic gates are the fundamental building blocks of latches. since there is no synchronization and clock signal used. hence, the latches operate immediately on the application of input signals.

characteristics of latches

some key characteristics of latches are explained below −

latches can store 1-bit of digital information that can be represented using either logic 0 or logic 1. thus, the latches are mainly used as memory elements in digital circuits.
latches have a feedback mechanism that allows them to maintain their current state as it is until the next input is applied.
the operation of latches is completely controlled by applied inputs that means the output of the latches updates based on the change in the input signals.

types of latches

the following are the main types of latches that used in digital circuits and systems −

sr latch
jk latch
d latch
t latch

let us now discuss about each type of latch in detail.

sr latch

the sr latch is a type of latch which has two input lines designated as s and r. where, s represents the set input and r represents the reset input. thus, it is also known as set-reset latch.

the sr latch has two stable states namely set state (s) and reset state (r). the block diagram of the sr latch is shown in the following figure.

in the case of sr latch, the s input sets the output q to 1 and q' to 0. on the other hand, the r input sets the output q to 0 and q' to 1. in case, when both s and r inputs are high, the latch is said to be in forbidden state.

the complete operation of the sr latch for different input combinations is described in the following truth table −

inputs		outputs		comment
s	r	q	q'	comment
0	0	q	q'	no change
0	1	0	1	reset state
1	0	1	0	set state
1	1	x	x	forbidden state

the sr latch can be implemented by connecting two nor gates in a cross-coupled manner as shown in the following figure.

jk latch

the jk latch is another type of latch which has two inputs namely, j and k. here, the input j is similar to s input and the input k is similar to r input in an sr latch.

the operation of the jk latch is similar to that of the sr latch but it does not have the forbidden state. instead, it has a toggle state in which the outputs q and q' swap their states when both inputs j and k are 1.

therefor, the jk latch is mainly designed to overcome the problem of forbidden state in the sr latch.

the block diagram of the jk latch is shown in the following figure −

the truth table given below describes the operation of the jk latch for different input combinations −

inputs		outputs		comment
j	k	q	q'	comment
0	0	q	q'	no change
0	1	0	1	reset state
1	0	1	0	set state
1	1	q'	q	toggle state

from this truth table, it is clear that the problem of forbidden state is addressed by implementing the toggle state.

the logic circuit of the jk latch consists of a combination of two nor gates and two and gates as shown in the following figure.

d latch

the d latch, also known as data latch or transparent latch, is a type of bistable multivibrator which has two input signals namely, d (data) input and e (enable) input.

the output q of the d latch is same as the input applied at the d input line as long as the e input is high. when the e input goes low, the output of the d latch is held as it is until the new input is applied to the d input.

the block diagram of the d latch is shown in the following figure.

the truth table given below explains the operation of the d latch −

inputs		outputs		comment
d	e	q	q'	comment
0	0	q	q'	no change
0	1	0	1	reset state
1	0	q	q'	no change
1	1	1	0	set state

the logic circuit diagram of the d latch is depicted in the following figure −

t latch

t latch is a type of latch that toggles its output state (q) when a logic 1 is applied to its input line. hence, it is also known as toggle latch.

the t latch is implemented by connecting the j and k inputs of the jk latch together as shown in the following block diagram.

the truth table describing the operation of the t latch is shown below −

input	present state		next state
t	q	q'	q	q'
0	0	1	0	1
0	1	0	1	0
1	0	1	1	0
1	1	0	0	1

the logic circuit diagram of the t latch is shown in the following figure −

applications of latches

the latches find several applications in the field of digital electronics. they are most elementary storage components used to store one bit of information in digital systems.

some of the common applications of latches are listed here −

latches are used as 1-bit memory element in digital systems.
latches are used to design digital registers which are employed for storage and manipulation of data in microprocessors and microcontrollers.
latches are used to design flip-flops which are basically the synchronized latches.
latches are also used in communication systems for temporary data storage or buffering purposes.

conclusion

in this chapter, we explained different types of latches used in digital systems along with some examples of applications of latches.

in conclusion, a latch is a 1-bit storage device made up of logic gates. it is a type of asynchronous sequential logic circuit which do not have a clocked signal for synchronization.

in digital systems, latches are used to serve some key functions like temporary data storage, data flow control, etc.

a flip-flop is a sequential digital electronic circuit having two stable states that can be used to store one bit of binary data. flip-flops are the fundamental building blocks of all memory devices.

types of flip-flops

s-r flip-flop
j-k flip-flop
d flip-flop
t flip-flop

s-r flip-flop

this is the simplest flip-flop circuit. it has a set input (s) and a reset input (r). when in this circuit when s is set as active, the output q would be high and the q' will be low. if r is set to active then the output q is low and the q' is high. once the outputs are established, the results of the circuit are maintained until s or r get changed, or the power is turned off.

truth table of s-r flip-flop

s	r	q	state
0	0	0	no change
0	1	0	reset
1	0	1	set
1	1	x

characteristics table of s-r flip-flop

s	r	q(t)	q(t+1)
0	0	0	0
0	0	1	1
0	1	0	0
0	1	1	0
1	0	0	1
1	0	1	1
1	1	0	x
1	1	1	x

characteristics equation of s-r flip-flop

$$\mathrm{q(t \: + \: 1) \: = \: s \: + \: r' \: q(t)}$$

j-k flip-flop

because of the invalid state corresponding to s=r=1 in the sr flip-flop, there is a need of another flip-flop. the jk flip-flop operates with only positive or negative clock transitions. the operation of the jk flip-flop is similar to the sr flip-flop. when the input j and k are different then the output q takes the value of j at the next clock edge.

when j and k both are low then no change occurs at the output. if both j and k are high, then at the clock edge, the output will toggle from one state to the other.

truth table of jk flip-flop

j	k	q	state
0	0	0	no change
0	1	0	reset
1	0	1	set
1	1	toggles	toggle

characteristics table of jk flip-flop

j	k	q(t)	q(t+1)
0	0	0	0
0	0	1	1
0	1	0	0
0	1	1	0
1	0	0	1
1	0	1	1
1	1	0	1
1	1	1	0

characteristics equation of jk flip-flop

$$\mathrm{q(t \: + \: 1) \: = \: j \: k \: q(t)' \: + \: k'q(t)}$$

d flip-flop

in a d flip-flop, the output can only be changed at positive or negative clock transitions, and when the inputs changed at other times, the output will remain unaffected. the d flip-flops are generally used for shift-registers and counters. the change in output state of d flip-flop depends upon the active transition of clock. the output (q) is same as input and changes only at active transition of clock

truth table of d flip-flop

d	q
0	0
1	1

characteristics equation of d flip-flops

$$\mathrm{q(t \: + \: 1) \: = \: d}$$

t flip-flop

a t flip-flop (toggle flip-flop) is a simplified version of jk flip-flop. the t flop is obtained by connecting the j and k inputs together. the flip-flop has one input terminal and clock input. these flip-flops are said to be t flip-flops because of their ability to toggle the input state. toggle flip-flops are mostly used in counters.

truth table of t flip-flop

t	q(t)	q(t+1)
0	0	0
0	1	1
1	0	1
1	1	0

characteristics equation of t flip-flop

$$\mathrm{q(t \: + \: 1) \: = \: t'q(t) \: + \: tq(t)' \: = \: t \: \oplus \: q(t)}$$

applications of flip-flops

counters
shift registers
storage registers, etc.

in previous chapter, we discussed the four flip-flops, namely sr flip-flop, d flip-flop, jk flip-flop & t flip-flop. we can convert one flip-flop into the remaining three flip-flops by including some additional logic. so, there will be total of twelve flip-flop conversions.

follow these steps for converting one flip-flop to the other.

consider the characteristic table of desired flip-flop.
fill the excitation values (inputs) of given flip-flop for each combination of present state and next state. the excitation table for all flip-flops is shown below.

present state	next state	sr flip-flop inputs		d flip-flop input	jk flip-flop inputs		t flip-flop input
q(t)	q(t+1)	s	r	d	j	k	t
0	0	0	x	0	0	x	0
0	1	1	0	1	1	x	1
1	0	0	1	0	x	1	1
1	1	x	0	1	x	0	0

get the simplified expressions for each excitation input. if necessary, use kmaps for simplifying.

draw the circuit diagram of desired flip-flop according to the simplified expressions using given flip-flop and necessary logic gates.

now, let us convert few flip-flops into other. follow the same process for remaining flipflop conversions.

sr flip-flop to other flip-flop conversions

following are the three possible conversions of sr flip-flop to other flip-flops.

sr flip-flop to d flip-flop
sr flip-flop to jk flip-flop
sr flip-flop to t flip-flop

sr flip-flop to d flip-flop conversion

here, the given flip-flop is sr flip-flop and the desired flip-flop is d flip-flop. therefore, consider the following characteristic table of d flip-flop.

d flip-flop input	present state	next state
d	q(t)	q(t + 1)
0	0	0
0	1	0
1	0	1
1	1	1

we know that sr flip-flop has two inputs s & r. so, write down the excitation values of sr flip-flop for each combination of present state and next state values. the following table shows the characteristic table of d flip-flop along with the excitation inputs of sr flip-flop.

d flip-flop input	present state	next state	sr flip-flop inputs
d	q(t)	q(t + 1)	s	r
0	0	0	0	x
0	1	0	0	1
1	0	1	1	0
1	1	1	x	0

from the above table, we can write the boolean functions for each input as below.

$$\mathrm{s \: = \: m_{2} \: + \: d_{3}}$$

$$\mathrm{r \: = \: m_{1} \: + \: d_{0}}$$

we can use 2 variable k-maps for getting simplified expressions for these inputs. the k-maps for s & r are shown below.

so, we got s = d & r = d' after simplifying. the circuit diagram of d flip-flop is shown in the following figure.

this circuit consists of sr flip-flop and an inverter. this inverter produces an output, which is complement of input, d. so, the overall circuit has single input, d and two outputs q(t) & q(t)'. hence, it is a d flip-flop. similarly, you can do other two conversions.

d flip-flop to other flip-flop conversions

following are the three possible conversions of d flip-flop to other flip-flops.

d flip-flop to t flip-flop
d flip-flop to sr flip-flop
d flip-flop to jk flip-flop

d flip-flop to t flip-flop conversion

here, the given flip-flop is d flip-flop and the desired flip-flop is t flip-flop. therefore, consider the following characteristic table of t flip-flop.

t flip-flop input	present state	next state
t	q(t)	q(t + 1)
0	0	0
0	1	1
1	0	1
1	1	0

we know that d flip-flop has single input d. so, write down the excitation values of d flip-flop for each combination of present state and next state values. the following table shows the characteristic table of t flip-flop along with the excitation input of d flip-flop.

t flip-flop input	present state	next state	d flip-flop input
t	q(t)	q(t + 1)	d
0	0	0	0
0	1	1	1
1	0	1	1
1	1	0	0

from the above table, we can directly write the boolean function of d as below.

$$\mathrm{d \: = \: t \: \oplus \: q \: \left ( t \: \right )}$$

so, we require a two input exclusive-or gate along with d flip-flop. the circuit diagram of t flip-flop is shown in the following figure.

this circuit consists of d flip-flop and an exclusive-or gate. this exclusive-or gate produces an output, which is ex-or of t and q(t). so, the overall circuit has single input, t and two outputs q(t) & q(t). hence, it is a t flip-flop. similarly, you can do other two conversions.

jk flip-flop to other flip-flop conversions

following are the three possible conversions of jk flip-flop to other flip-flops.

jk flip-flop to t flip-flop
jk flip-flop to d flip-flop
jk flip-flop to sr flip-flop

jk flip-flop to t flip-flop conversion

here, the given flip-flop is jk flip-flop and the desired flip-flop is t flip-flop. therefore, consider the following characteristic table of t flip-flop.

t flip-flop input	present state	next state
t	q(t)	q(t + 1)
0	0	0
0	1	1
1	0	1
1	1	0

we know that jk flip-flop has two inputs j & k. so, write down the excitation values of jk flip-flop for each combination of present state and next state values. the following table shows the characteristic table of t flip-flop along with the excitation inputs of jk flipflop.

t flip-flop input	present state	next state	jk flip-flop inputs
t	q(t)	q(t + 1)	j	k
0	0	0	0	x
0	1	1	x	0
1	0	1	1	x
1	1	0	x	1

from the above table, we can write the boolean functions for each input as below.

$$\mathrm{j \: = \: m_{2} \: + \: d_{1} \: + \: d_{3}}$$

$$\mathrm{k \: = \: m_{3} \: + \: d_{0} \: + \: d_{2}}$$

we can use 2 variable k-maps for getting simplified expressions for these two inputs. the k-maps for j & k are shown below.

so, we got, j = t & k = t after simplifying. the circuit diagram of t flip-flop is shown in the following figure.

circuit diagram of t flip-flop with jk flip-flop

this circuit consists of jk flip-flop only. it doesnt require any other gates. just connect the same input t to both j & k. so, the overall circuit has single input, t and two outputs q(t) & q(t). hence, it is a t flip-flop. similarly, you can do other two conversions.

t flip-flop to other flip-flop conversions

following are the three possible conversions of t flip-flop to other flip-flops.

t flip-flop to d flip-flop
t flip-flop to sr flip-flop
t flip-flop to jk flip-flop

t flip-flop to d flip-flop conversion

here, the given flip-flop is t flip-flop and the desired flip-flop is d flip-flop. therefore, consider the characteristic table of d flip-flop and write down the excitation values of t flip-flop for each combination of present state and next state values. the following table shows the characteristic table of d flip-flop along with the excitation input of t flip-flop.

d flip-flop input	present state	next state	t flip-flop input
d	q(t)	q(t + 1)	t
0	0	0	0
0	1	0	1
1	0	1	1
1	1	1	0

from the above table, we can directly write the boolean function of t as below.

$$\mathrm{t \: = \: d \: \oplus \: q \left ( t \right )}$$

so, we require a two input exclusive-or gate along with t flip-flop. the circuit diagram of d flip-flop is shown in the following figure.

this circuit consists of t flip-flop and an exclusive-or gate. this exclusive-or gate produces an output, which is ex-or of d and q(t). so, the overall circuit has single input, d and two outputs q(t) & q(t). hence, it is a d flip-flop. similarly, you can do other two conversions.

flip-flop is a 1 bit memory cell which can be used for storing the digital data. to increase the storage capacity in terms of number of bits, we have to use a group of flip-flop. such a group of flip-flop is known as a register. the n-bit register will consist of n number of flip-flop and it is capable of storing an n-bit word.

the binary data in a register can be moved within the register from one flip-flop to another. the registers that allow such data transfers are called as shift registers. there are four mode of operations of a shift register.

serial in - serial out (siso) shift register
serial in - parallel out (sipo) shift register
parallel in - serial out (piso) shift register
parallel in - parallel out (pipo) shift register

serial in - serial out (siso) shift register

let all the flip-flop be initially in the reset condition i.e. q₃ = q₂ = q₁ = q₀ = 0. if an entry of a four bit binary number 1 1 1 1 is made into the register, this number should be applied to d_in bit with the lsb bit applied first. the d input of ff-3 i.e. d₃ is connected to serial data input d_in. output of ff-3 i.e. q₃ is connected to the input of the next flip-flop i.e. d₂ and so on.

block diagram

operation

before application of clock signal, let q₃ q₂ q₁ q₀ = 0000 and apply lsb bit of the number to be entered to d_in. so d_in = d₃ = 1. apply the clock. on the first falling edge of clock, the ff-3 is set, and stored word in the register is q₃ q₂ q₁ q₀ = 1000.

apply the next bit to d_in. so d_in = 1. as soon as the next negative edge of the clock hits, ff-2 will set and the stored word change to q₃ q₂ q₁ q₀ = 1100.

apply the next bit to be stored i.e. 1 to d_in. apply the clock pulse. as soon as the third negative clock edge hits, ff-1 will be set and output will be modified to q₃ q₂ q₁ q₀ = 1110.

similarly with d_in = 1 and with the fourth negative clock edge arriving, the stored word in the register is q₃ q₂ q₁ q₀ = 1111.

truth table

waveforms

serial in - parallel out (sipo) shift register

in such types of operations, the data is entered serially and taken out in parallel fashion.
data is loaded bit by bit. the outputs are disabled as long as the data is loading.
as soon as the data loading gets completed, all the flip-flops contain their required data, the outputs are enabled so that all the loaded data is made available over all the output lines at the same time.
4 clock cycles are required to load a four bit word. hence the speed of operation of sipo mode is same as that of siso mode.

block diagram

parallel in - serial out (piso) shift register

data bits are entered in parallel fashion.
the circuit shown below is a four bit parallel input serial output register.
output of previous flip flop is connected to the input of the next one via a combinational circuit.
the binary input word b₀, b₁, b₂, b₃ is applied though the same combinational circuit.
there are two modes in which this circuit can work namely - shift mode or load mode.

load mode

when the shift/load bar line is low (0), the and gate 2, 4 and 6 become active they will pass b₁, b₂, b₃ bits to the corresponding flip-flops. on the low going edge of clock, the binary input b₀, b₁, b₂, b₃ will get loaded into the corresponding flip-flops. thus parallel loading takes place.

shift mode

when the shift/load bar line is low (1), the and gate 2, 4 and 6 become inactive. hence the parallel loading of the data becomes impossible. but the and gate 1,3 and 5 become active. therefore the shifting of data from left to right bit by bit on application of clock pulses. thus the parallel in serial out operation takes place.

block diagram

parallel in - parallel out (pipo) shift register

in this mode, the 4 bit binary input b₀, b₁, b₂, b₃ is applied to the data inputs d₀, d₁, d₂, d₃ respectively of the four flip-flops. as soon as a negative clock edge is applied, the input binary bits will be loaded into the flip-flops simultaneously. the loaded bits will appear simultaneously to the output side. only clock pulse is essential to load all the bits.

block diagram

bidirectional shift register

if a binary number is shifted left by one position then it is equivalent to multiplying the original number by 2. similarly if a binary number is shifted right by one position then it is equivalent to dividing the original number by 2.
hence if we want to use the shift register to multiply and divide the given binary number, then we should be able to move the data in either left or right direction.
such a register is called bi-directional register. a four bit bi-directional shift register is shown in fig.
there are two serial inputs namely the serial right shift data input dr, and the serial left shift data input dl along with a mode select input (m).

block diagram

operation

sr.no

condition

operation

with m = 1 − shift right operation

if m = 1, then the and gates 1, 3, 5 and 7 are enabled whereas the remaining and gates 2, 4, 6 and 8 will be disabled.

the data at d_r is shifted to right bit by bit from ff-3 to ff-0 on the application of clock pulses. thus with m = 1 we get the serial right shift operation.

with m = 0 − shift left operation

when the mode control m is connected to 0 then the and gates 2, 4, 6 and 8 are enabled while 1, 3, 5 and 7 are disabled.

the data at d_l is shifted left bit by bit from ff-0 to ff-3 on the application of clock pulses. thus with m = 0 we get the serial right shift operation.

universal shift register

a shift register which can shift the data in only one direction is called a uni-directional shift register. a shift register which can shift the data in both directions is called a bi-directional shift register. applying the same logic, a shift register which can shift the data in both directions as well as load it parallely, is known as a universal shift register. the shift register is capable of performing the following operation −

parallel loading
left shifting
right shifting

the mode control input is connected to logic 1 for parallel loading operation whereas it is connected to 0 for serial shifting. with mode control pin connected to ground, the universal shift register acts as a bi-directional register. for serial left operation, the input is applied to the serial input which goes to and gate-1 shown in figure. whereas for the shift right operation, the serial input is applied to d input.

block diagram

in previous chapter, we discussed four types of shift registers. based on the requirement, we can use one of those shift registers. following are the applications of shift registers.

shift register is used as parallel to serial converter, which converts the parallel data into serial data. it is utilized at the transmitter section after analog to digital converter (adc) block.

shift register is used as serial to parallel converter, which converts the serial data into parallel data. it is utilized at the receiver section before digital to analog converter (dac) block.

shift register along with some additional gate(s) generate the sequence of zeros and ones. hence, it is used as sequence generator.

shift registers are also used as counters. there are two types of counters based on the type of output from right most d flip-flop is connected to the serial input. those are ring counter and johnson ring counter.

in this chapter, let us discuss about these two counters one by one.

ring counter

in previous chapter, we discussed the operation of serial in - parallel out (sipo) shift register. it accepts the data from outside in serial form and it requires n clock pulses in order to shift n bit data.

similarly, n bit ring counter performs the similar operation. but, the only difference is that the output of rightmost d flip-flop is given as input of leftmost d flip-flop instead of applying data from outside. therefore, ring counter produces a sequence of states (pattern of zeros and ones) and it repeats for every n clock cycles.

the block diagram of 3-bit ring counter is shown in the following figure.

the 3-bit ring counter contains only a 3-bit sipo shift register. the output of rightmost d flip-flop is connected to serial input of left most d flip-flop.

assume, initial status of the d flip-flops from leftmost to rightmost is $\mathrm{q_{2}q_{1}q_{0} \: = \: 001}$. here, $\mathrm{q_{2}}$ & $\mathrm{q_{0}}$ are msb & lsb respectively. we can understand the working of ring counter from the following table.

no of positive edge of clock	serial input = q₀	q₂(msb)	q₁	q₀(lsb)
0	-	0	0	1
1	1	1	0	0
2	0	0	1	0
3	0	0	0	1

the initial status of the d flip-flops in the absence of clock signal is $\mathrm{q_{2}q_{1}q_{0} \: = \: 001}$. this status repeats for every three positive edge transitions of clock signal.

therefore, the following operations take place for every positive edge of clock signal.

serial input of first d flip-flop gets the previous output of third flip-flop. so, the present output of first d flip-flop is equal to the previous output of third flip-flop.

the previous outputs of first and second d flip-flops are right shifted by one bit. that means, the present outputs of second and third d flip-flops are equal to the previous outputs of first and second d flip-flops.

johnson ring counter

the operation of johnson ring counter is similar to that of ring counter. but, the only difference is that the complemented output of rightmost d flip-flop is given as input of leftmost d flip-flop instead of normal output. therefore, n bit johnson ring counter produces a sequence of states (pattern of zeros and ones) and it repeats for every 2n clock cycles.

johnson ring counter is also called as twisted ring counter and switch tail ring counter. the block diagram of 3-bit johnson ring counter is shown in the following figure.

the 3-bit johnson ring counter also contains only a 3-bit sipo shift register. the complemented output of rightmost d flip-flop is connected to serial input of left most d flip-flop.

assume, initially all the d flip-flops are cleared. so, $\mathrm{q_{2}q_{1}q_{0} \: = \: 000}$. here, $\mathrm{q_{2}}$ & $\mathrm{q_{0}}$ are msb & lsb respectively. we can understand the working of johnson ring counter from the following table.

no of positive edge of clock	serial input = q₀	q₂(msb)	q₁	q₀(lsb)
0	-	0	0	0
1	1	1	0	0
2	1	1	1	0
3	1	1	1	1
4	0	0	1	1
5	0	0	0	1
6	0	0	0	0

the initial status of the d flip-flops in the absence of clock signal is $\mathrm{q_{2}q_{1}q_{0} \: = \: 000}$. this status repeats for every six positive edge transitions of clock signal.

therefore, the following operations take place for every positive edge of clock signal.

serial input of first d flip-flop gets the previous complemented output of third flip-flop. so, the present output of first d flip-flop is equal to the previous complemented output of third flip-flop.

counter is a sequential circuit. a digital circuit which is used for a counting pulses is known counter. counter is the widest application of flip-flops. it is a group of flip-flops with a clock signal applied. counters are of two types.

asynchronous or ripple counters
synchronous counters

asynchronous or ripple counters

the logic diagram of a 2-bit ripple up counter is shown in figure. the toggle (t) flip-flop are being used. but we can use the jk flip-flop also with j and k connected permanently to logic 1. external clock is applied to the clock input of flip-flop a and q_a output is applied to the clock input of the next flip-flop i.e. ff-b.

logical diagram

logic diagram of asynchronous or ripple counters

operation

sr.no	condition	operation
1	initially let both the ffs be in the reset state	q_bq_a = 00 initially
2	after 1st negative clock edge	as soon as the first negative clock edge is applied, ff-a will toggle and q_a will be equal to 1. q_a is connected to clock input of ff-b. since q_a has changed from 0 to 1, it is treated as the positive clock edge by ff-b. there is no change in q_b because ff-b is a negative edge triggered ff. q_bq_a = 01 after the first clock pulse.
3	after 2nd negative clock edge	on the arrival of second negative clock edge, ff-a toggles again and q_a = 0. the change in q_a acts as a negative clock edge for ff-b. so it will also toggle, and q_b will be 1. q_bq_a = 10 after the second clock pulse.
4	after 3rd negative clock edge	on the arrival of 3rd negative clock edge, ff-a toggles again and q_a become 1 from 0. since this is a positive going change, ff-b does not respond to it and remains inactive. so q_b does not change and continues to be equal to 1. q_bq_a = 11 after the third clock pulse.
5	after 4th negative clock edge	on the arrival of 4th negative clock edge, ff-a toggles again and q_a becomes 1 from 0. this negative change in q_a acts as clock pulse for ff-b. hence it toggles to change q_b from 1 to 0. q_bq_a = 00 after the fourth clock pulse.

truth table

synchronous counters

if the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such a counter is called as synchronous counter.

2-bit synchronous up counter

the j_a and k_a inputs of ff-a are tied to logic 1. so ff-a will work as a toggle flip-flop. the j_b and k_b inputs are connected to q_a.

logical diagram

operation

sr.no	condition	operation
1	initially let both the ffs be in the reset state	q_bq_a = 00 initially.
2	after 1st negative clock edge	as soon as the first negative clock edge is applied, ff-a will toggle and q_a will change from 0 to 1. but at the instant of application of negative clock edge, q_a , j_b = k_b = 0. hence ff-b will not change its state. so q_b will remain 0. q_bq_a = 01 after the first clock pulse.
3	after 2nd negative clock edge	on the arrival of second negative clock edge, ff-a toggles again and q_a changes from 1 to 0. but at this instant q_a was 1. so j_b = k_b= 1 and ff-b will toggle. hence q_b changes from 0 to 1. q_bq_a = 10 after the second clock pulse.
4	after 3rd negative clock edge	on application of the third falling clock edge, ff-a will toggle from 0 to 1 but there is no change of state for ff-b. q_bq_a = 11 after the third clock pulse.
5	after 4th negative clock edge	on application of the next clock pulse, q_a will change from 1 to 0 as q_b will also change from 1 to 0. q_bq_a = 00 after the fourth clock pulse.

classification of counters

depending on the way in which the counting progresses, the synchronous or asynchronous counters are classified as follows −

up counters
down counters
up/down counters

up/down counter

up counter and down counter is combined together to obtain an up/down counter. a mode control (m) input is also provided to select either up or down mode. a combinational circuit is required to be designed and used between each pair of flip-flop in order to achieve the up/down operation.

type of up/down counters

there are two types of up/down counters −

up/down ripple counters
up/down synchronous counter

up/down ripple counters

in the up/down ripple counter all the ffs operate in the toggle mode. so either t flip-flops or jk flip-flops are to be used. the lsb flip-flop receives clock directly. but the clock to every other ff is obtained from (q = q bar) output of the previous ff.

up counting mode (m=0) − the q output of the preceding ff is connected to the clock of the next stage if up counting is to be achieved. for this mode, the mode select input m is at logic 0 (m=0).
down counting mode (m=1) − if m = 1, then the q bar output of the preceding ff is connected to the next ff. this will operate the counter in the counting mode.

example

3-bit binary up/down ripple counter.

3-bit − hence three ffs are required.
up/down − so a mode control input is essential.
for a ripple up counter, the q output of preceding ff is connected to the clock input of the next one.
for a ripple up counter, the q output of preceding ff is connected to the clock input of the next one.
for a ripple down counter, the q bar output of preceding ff is connected to the clock input of the next one.
let the selection of q and q bar output of the preceding ff be controlled by the mode control input m such that, if m = 0, up counting. so connect q to clk. if m = 1, down counting. so connect q bar to clk.

block diagram

truth table

operation

sr.no

condition

operation

case 1 − with m = 0 (up counting mode)

if m = 0 and m bar = 1, then the and gates 1 and 3 in fig. will be enabled whereas the and gates 2 and 4 will be disabled.

hence q_a gets connected to the clock input of ff-b and q_b gets connected to the clock input of ff-c.

these connections are same as those for the normal up counter. thus with m = 0 the circuit work as an up counter.

case 2 − with m = 1 (down counting mode)

if m = 1, then and gates 2 and 4 in fig. are enabled whereas the and gates 1 and 3 are disabled.

hence q_a bar gets connected to the clock input of ff-b and q_b bar gets connected to the clock input of ff-c.

these connections will produce a down counter. thus with m = 1 the circuit works as a down counter.

modulus counter (mod-n counter)

the 2-bit ripple counter is called as mod-4 counter and 3-bit ripple counter is called as mod-8 counter. so in general, an n-bit ripple counter is called as modulo-n counter. where, mod number = 2ⁿ.

type of modulus

2-bit up or down (mod-4)
3-bit up or down (mod-8)
4-bit up or down (mod-16)

application of counters

frequency counters
digital clock
time measurement
a to d converter
frequency divider circuits
digital triangular wave generator.

finite state machines are the fundamental building blocks of various digital and computing systems. they provide a systematic approach to model the behavior of sequential circuits. they also help to control various processes in digital systems.

read this chapter to learn the components, types, advantages, and applications of finite state machines.

what is a finite state machine?

a finite state machine (fsm) is a mathematical model that is used to explain and understand the behavior of a digital system. more specifically, it is a structured and systematic model that helps to understand the behavior of a sequential circuit that exists in a finite number of states at a given point of time.

in more simple words, a synchronous sequential circuit is also called as finite state machine fsm, if it has a finite number of states.

the transition of these finite states takes place based on the internal or external inputs that results in the predictable and systematic changes in the behavior of the system.

components of a finite state machine

a typical finite state machine consists of the following main components −

finite states

the finite states are nothing but the distinct modes or conditions in the given system. each of these finite states represents a specific behavior. in digital system representation, these finite states are generally represented through symbols or labels.

state transitions

in terms of finite state machines, the state transition can be defined as the change from one state to another. this change in state or state transition takes placed based on some specific inputs or conditions. these state transitions are generally triggered by events which are associated with some rules or conditions and determine the next state of the system.

state diagram

the state transition and the behavior of a finite state machine can be represented in a graphical form that is known as state diagram of the finite state machine.

inputs

the inputs to the finite state machines are the external signals that trigger the state transitions in the system. these inputs are to be entered into the finite state machine by using sensors, user input devices like mic, keyboard, etc.

outputs

the results produced by the system as per the inputs and current states are known as outputs. these outputs of the system can be used to trigger events, control actuators, or to provide feedback to the external environment.

types of finite state machine

there are two types of finite state machines namely,

mealy state machine
moore state machine

let us now discuss these two types of finite state machines in detail.

mealy state machine

a finite state machine is said to be a mealy state machine, if its outputs depend on both present inputs & present states. the block diagram of the mealy state machine is shown in the following figure −

as shown in the figure, there are two main parts presents in the mealy state machine. those are combinational logic circuit and memory element. the memory element is useful to provide some part of previous outputs and present states as inputs to the combinational logic circuit.

based on the present inputs and present states, the mealy state machine produces outputs. therefore, the outputs will be valid only at positive or negative transition of the clock signal.

state diagram of mealy state machine

the state diagram of mealy state machine is shown in the following figure.

in the above figure, there are three states, namely a, b and c. these states are labelled inside the circles and each circle corresponds to one state. state transitions between these states are represented with directed lines. here, 0 / 0, 1 / 0 and 1 / 1 denote the input / output. in the above figure, there are two state transitions from each state based on the value of input.

in general, the number of states required in mealy state machine is less than or equal to the number of states required in moore state machine. there is an equivalent moore state machine for each mealy state machine.

moore state machine

a finite state machine is said to be a moore state machine, if its outputs depend only on the present states.

the block diagram of the moore state machine is shown in the following figure −

as shown in above figure, there are two parts presents in a moore state machine. those are combinational logic and memory. in this case, the present inputs and present states determine the next states. so, based on next states, moore state machine produces the outputs. therefore, the outputs will be valid only after transition of the state.

state diagram of moore state machine

the state diagram of moore state machine is shown in the following figure −

in the above figure, there are four states, namely a, b, c, and d. these states and the respective outputs are labelled inside the circles. here, only the input value is labeled on each transition. in the above figure, there are two transitions from each state based on the value of input.

in general, the number of states required in moore state machine is more than or equal to the number of states required in mealy state machine. there is an equivalent mealy state machine for each moore state machine. so, based on the requirement we can use one of them.

advantages of finite state machine

the finite state machines have several advantages in the field of digital electronics. all these advantages make them a crucial tool for modeling and implementing various digital systems. some key advantages of finite state machines are listed below −

finite state machines provide a simple and systematic way to model and understand the behavior of digital systems with discrete finite states and transitions between them.
finite state machines support modular designs that help to breakdown the complex digital systems into smaller components. each component of the finite state machine can represent a specific task of the entire system. this allows for easier design, testing, and maintenance.
finite state machines provide ease in terms of scalability that allows for addition of new states and transitions, and logics to the existing system without altering its fundamental structure or operation. this becomes essential when the system requirement evolve or expand.
fundamentally, finite state machines have a deterministic or predictable behavior. that means, we can easily determine the next state of the system from its current state and the inputs. this predictable behavior helps us to ensure the reliable and consistent operation of the system. it also makes the finite state machines best suited for real-time and safety-critical applications.
finite state machines are considered highly efficient in terms of both hardware and software implementations, as they require minimal hardware and software resources such as logic gates, memory, and other processing resources.
finite state machines support parallelism. this technology allows the occurrence of multiple states and state transitions simultaneously within the system. it also optimizes the performance and improves the responsiveness of the system.
finite state machines are versatile tools in the field of digital electronics and computer science, as they find their applications in various fields such as digital system design, control system design, software development, development of artificial intelligence, etc.

applications of finite state machine

in the field of digital electronics and computer science, the finite state machines are used in various applications due to their ability to model sequential logic systems effectively. here are some examples of applications of finite state machines −

finite state machines are commonly used in designing and implementation of different types of sequential logic circuits, such as digital counters, timers, control units, etc.
finite state machines are used in digital control systems to control and regulate the behavior of complex automated systems, like robots, industrial control and automation systems, etc.
finite state machines are used in the implementation of communication protocols like network protocols and state-based digital systems like data transmission and protocol converters.
finite state machines are also used in the field of software development to model and define the behavior of state-based systems in applications, to create user interfaces, to implement game mechanics, and to develop workflow management systems.

conclusion

in conclusion, finite state machines are important and powerful tools used in the field of digital electronics to model, design, and analyze the behavior of state-based digital systems and synchronous sequential circuits.

finite state machines allow engineers and system designers to design and implement efficient, reliable, and scalable systems that can handle complex state-based logics and processes in the field of digital electronics and computer engineering.

every digital system can be partitioned into two parts. those are data path (digital) circuits and control circuits. data path circuits perform the functions such as storing of binary information (data) and transfer of data from one system to the other system. whereas, control circuits determine the flow of operations of digital circuits.

it is difficult to describe the behavior of large state machines using state diagrams. to overcome this difficulty, algorithmic state machine (asm) charts can be used. asm charts are similar to flow charts. they are used to represent the flow of tasks to be performed by data path circuits and control circuits.

basic components of asm charts

following are the three basic components of asm charts.

state box
decision box
conditional output box

state box

state box is represented in rectangular shape. each state box represents one state of the sequential circuit. the symbol of state box is shown in the following figure.

it is having one entry point and one exit point. name of the state is placed to the left of state box. the unconditional outputs corresponding to that state can be placed inside state box. moore state machine outputs can also be placed inside state box.

decision box

decision box is represented in diamond shape. the symbol of decision box is shown in the following figure.

it is having one entry point and two exit paths. the inputs or boolean expressions can be placed inside the decision box, which are to be checked whether they are true or false. if the condition is true, then it will prefer path1. otherwise, it will prefer path2.

conditional output box

conditional output box is represented in oval shape. the symbol of conditional output box is shown in the following figure.

it is also having one entry point and one exit point similar to state box. the conditional outputs can be placed inside state box. in general, mealy state machine outputs are represented inside conditional output box. so, based on the requirement, we can use the above components properly for drawing asm charts.

an analog-to-digital converter, also known as adc, is a digital circuit used to convert analog signals into digital format.

the conversion of analog signals into digital format is crucial for their processing with the help of digital systems like microprocessors, microcontrollers, digital signal processors (dsps), etc. therefore, adcs are important components in several digital systems like computers and other digital devices.

in this chapter, we will explain in detail the concept, components, types, and applications of analog to digital converters.

what is an analog to digital converter?

an analog to digital converter is a digital circuit designed to perform conversion of analog signals into digital data format. it is also known adc. analog to digital converters are essential components in digital systems like computers, data processors, digital communication systems, etc.

the following figure depicts the block diagram of an analog to digital converter −

from this figure, it is clear that the input to an analog to digital converter is an analog or natural signal and the output is a digital or discrete time signal.

in practical systems, the analog to digital converter serves as an interface between external environment and a digital system.

working of analog to digital converter

the working of an analog to digital converter involves the processes explained below −

inputting analog signal

an analog to digital converter takes an analog signal as input. the analog signal could be a voltage, current, temperature, pressure, or any other physical quantity that changes continuously with time.

sampling

at this stage, the analog to digital converter samples the input analog signal at regular intervals of time. these time intervals are defined in terms of sampling rate.

in the sampling process, the analog signal that varies continuously over time is measured at discrete instants of time to collect discrete values of the signal.

quantization

quantization is a process of assigning a digital or discrete value to each sampled value of the analog signal. in the process of quantization, the range of all possible analog values is divided into a finite number of discrete digital values.

encoding

encoding is a process of converting the quantized digital values into their equivalent binary numbers. these encoded binary numbers represent the sampled analog values in the digital format.

the resolution, accuracy, and precision of the analog to digital converter is determined by the number of bits used for encoding.

outputting digital signal

at the end, the analog to digital converter produces a digital signal as output. this output digital signal can be processed, stored, or transmitted by digital systems.

performance factors of analog to digital converters

the performance of an analog to digital converter can be evaluated using several different factors. the following two are the most important −

signal-to-noise ratio (snr) of adc

the signal-to-noise ratio (snr) of an analog to digital converter is defined as the measure of ability of the converter to differentiate between the desired signal and unwanted noise signal.

mathematically, the snr of an analog to digital converter is expressed as the ratio of the power of the electrical signal (that represents the useful information) to the power of the noise signal (that represents the unwanted disturbances).

in practice, the snr is expressed in decibels (db) and the formula for calculating the snr of an adc is given below,

$$\mathrm{snr \: of \: adc \: = \: 10 \: \times \: log ( \frac{electrical \: signal \: power}{noise \: signal \: power})}$$

from this expression, it is clear that a higher snr represents better performance of the analog to digital converter. in other words, an analog to digital converter having a high snr distinguishes the electrical signal from the noise signal more clearly. therefore, it is desirable that the analog to digital converter have a high snr so that it can accurately capture and digitalize smaller analog signals even in the presence of noise signals.

bandwidth of analog to digital converter

the bandwidth of an analog to digital converter is nothing but the range of frequencies that it can sample and digitalize accurately. the sampling rate of the analog to digital converter determines its bandwidth. where, the sampling rate is defined as the number of samples of the analog signal taken per second.

according to the nyquist-shannon sampling theorem, the maximum sampling rate of an analog to digital converter should be at least double of the maximum frequency component present in the input analog signal. it is an important factor to avoid misidentification of the signal that can introduce distortion or error in sampling.

let us take an example to understand this, consider an analog to digital converter having a maximum sampling rate of 150 khz, then its bandwidth should be limited to frequencies less than 75 khz to prevent distortion.

hence, it is important that the analog to digital converter should have a sufficient bandwidth to capture the high-frequency analog signals accurately.

types of analog-to-digital converters

in digital electronics, different types of analog-to-digital converters (adcs) are designed to fulfil the requirements of different applications.some of common types of analog-to-digital converters include the following −

flash adc
semi-flash adc
successive approximation register adc
sigma-delta adc
pipelined adc

flash adc

flash adc, also known as direct adc, is the fastest adc available. this type of adc has sampling rates of the order of gigahertz. the flash adcs offer such high speeds because they use a bank of comparators that can operate in parallel, each for a certain voltage range.

however, the flash adcs are relatively larger in size and costlier than other types of adcs. also, they consume relatively more power. in the case of a flash adc, if "n bits" is resolution of the adc, then it requires (2ⁿ 1) comparators in its bank. for example, a flash adc having 8-bit resolution requires (2⁸ 1 = 255) comparators.

the flash analog-to-digital converters are mainly used in digitization of video signals or fast signals in optical storage.

semi-flash adc

the semi-flash adc is a type of analog-to-digital converter that combines the fast speed of a flash adc with a reduced number of comparators. these two features together make the semi-flash adc compact in size and cost effective as compared to a flash adc.

in a semi-flash analog to digital converter, two separate flash converters are used that operate in parallel. each converter has a resolution that is half the number of bits of the whole semi-flash adc. one converter handles the most significant bits (msbs) and the other converter handles the least significant bits (lsbs) of the signal.

after processing, the outputs produced by the two converters are combined to generate the final digital output of the semi-flash adc.

the most significant advantage of the semi-flash analog to digital converter is that it requires a lesser number of comparators than an ordinary flash adc with maintaining the high-speed operation. this results in smaller size, reduced complexity and cost. however, it takes more time to complete the conversion process because it requires some additional time to combine the partial results of the two separate converters.

the semi-flash analog-to-digital converters are widely used in applications that require a balance between speed, resolution, and cost.

successive approximation register adc

the successive approximation register analog to digital converter, abbreviated as sar adc, is a type of analog to digital converter that uses a series of comparisons to determine each bit of the digital output.

the sar adc starts working by initializing its internal approximation registers. then, it takes a sample of the input analog signal and stores it steady until the conversion process completes.

after that a binary search algorithm is utilized to perform approximation of the input signal. this process starts by setting the most significant bit (msb) of the output digital signal to the highest value and compares this value with the sampled input analog signal.

in the next step, the sar adc compares the sampled input analog signal with the output of an internal digital-to-analog converter that produces a signal proportional to the current approximation of the input signal.

depending on results of the comparison, the sar adc successively changes the value of each bit in the digital output until the desired output is obtained. once all bits of the digital output have been determined, the sar converter completes the conversion process. the digital output obtained represents the digital approximation of the sampled input analog signal.

the sar analog-to-digital converters are commonly used in various applications, such as consumer electronics, medical instruments, data acquisition systems, etc.

sigma-delta adc

the sigma-delta analog-to-digital converter, also represented as adc, is a type of analog to digital converter that provides a high resolution and is used in applications that require precise measurement and signal processing like in audio recording, high-quality audio systems, sensor-based systems, precise instruments, etc.

the working of a sigma-delta adc involves the following processes −

first, it samples the analog input signal at a frequency significantly higher than the nyquist rate to capture more information about the input signal. this process is called oversampling.

then, delta modulation is used to convert the oversampled analog signal into a series of digital pulses. in the process of delta modulation, the difference or delta between successive samples of the analog input signal is quantized and converted into digital form.

now, the sigma-delta modulation is performed, in which a sigma-delta modulator is used to modulate the difference between the actual analog signal and its digital form. in this modulation, the quantization noise is pushed away from the desired frequency band and towards the higher frequencies.

after sigma-delta modulation, the digital signal is passed through a low-pass filter that removes the high-frequency noise that can be introduced during oversampling and sigma-delta modulation. this low-pass filter produces a high-resolution digital output by extracting the low-frequency components.

at the end of the conversion process, the digital signal is down-sampled (i.e., decimated) to decrease its sample rate to the desired output rate.

pipelined adc

the pipelined analog to digital converter is a type of adc which is similar to the sar adc, but it performs a coarse and refined conversion. it provides a balance between resolution and speed that make it suitable to use in communication systems, medical test equipment, multimedia, industrial control systems, etc.

a pipelined adc works in multiple stages, where each stage completes a specific part of the analog-to-digital conversion. it is called pipelined adc because all stages take place in a pipeline manner, in which the output of one stage enters into the next stage.

in the pipelined adc, the analog input signal is divided into multiple subranges and each stage of the pipeline performs quantization of a subrange to convert the analog input signal into digital form. it is important to note that all stages of the pipelined adc operate in parallel to provide a faster conversion rate.

the pipelined adc uses various digital correction techniques such as digital calibration, error correction algorithms, and digital filtering to remove errors that can be introduced during the analog-to-digital conversion process. this improves the accuracy and reliability of the digital output.

this is all about some commonly used types of analog to digital converters (adcs) in digital electronics.

applications of analog to digital converter

analog-to-digital converters (adcs) are used in various industries and fields where analog signals have to be processed, analyzed, or transmitted using digital systems like computers. some common applications of analog to digital converters are listed below −

in the field of digital signal processing, adcs are used for converting analog signals obtained from sensors, microphones, or other analog devices into digital format for processing them using digital processors.
in audio processing applications, adcs are used to convert analog audio signals into digital format for storage, manipulation, and transmission in digital systems.
adcs are essential components in various data acquisition systems used in the field of scientific research, industrial automation, and instrumentation.
in communication systems, adcs are used to convert analog audio or video signals into digital format for transmission over communication channels.
adcs are used in radio receivers for digitization of received radio frequency (rf) signals.
adcs play an important role in several medical equipment and healthcare systems for converting various analog bio-signals and physiological parameters like heart rate, blood pressure, oxygen saturation, eeg signals, etc. into digital format to process them using digital systems.
in automotive electronics, adcs are used to convert analog signals received from sensors measuring parameters such as temperature, torque, speed, etc. into digital format for driver assistance and vehicle diagnostics.
adcs are also used in a wide range of consumer electronic devices such as smartphones, tablets, laptops, entertainment equipment, etc.

these are a few examples of the applications of analog-to-digital converters (adcs) in various fields and industries.

conclusion

in this chapter, we explained in detail about analog to digital converters, their types and applications. in conclusion, an analog to digital converter is an electronic circuit that can convert an analog input signal into a digital output signal.

adcs are important components in several devices and systems used across various industries. this is because, the signals received in real-time like voice signals, signals from sensors, etc. are analog in nature and they cannot be processed using digital systems like computers. adcs help to overcome this interfacing issue. basically, adcs act as an interface between an analog input device and a digital processing element.

a digital to analog converter (dac) converts a digital input signal into an analog output signal. the digital signal is represented with a binary code, which is a combination of bits 0 and 1 while the analog signal is a continuous time function.

this chapter deals with digital to analog converters in detail. the block diagram of dac is shown in the following figure −

a digital to analog converter (dac) consists of a number of binary inputs and a single output. in general, the number of binary inputs of a dac will be a power of two.

types of digital to analog converters

depending on the construction and structure, there are two types of digital to analog converters, they are −

weighted resistor dac
r-2r ladder dac

the following sections discuss about these two types of dacs in detail.

weighted resistor dac

a weighted resistor dac produces an analog output, which is almost equal to the digital (binary) input by using binary weighted resistors in the inverting adder circuit. in short, a binary weighted resistor dac is called as weighted resistor dac.

the circuit diagram of a 3-bit binary weighted resistor dac is shown in the following figure −

recall that the bits of a binary number can have only one of the two values. i.e., either 0 or 1. let the 3-bit binary input is b₂b₁b₀. here, the bits b₂ and b₀ denote the most significant bit (msb) and least significant bit (lsb) respectively.

the digital switches shown in the above figure will be connected to ground, when the corresponding input bits are equal to '0'. similarly, the digital switches shown in the above figure will be connected to the negative reference voltage, v_r when the corresponding input bits are equal to '1'.

in the above circuit, the non-inverting input terminal of an op-amp is connected to ground. that means zero volts is applied at the non-inverting input terminal of op-amp.

according to the virtual short concept, the voltage at the inverting input terminal of op-amp is same as that of the voltage present at its non-inverting input terminal. so, the voltage at the inverting input terminals node will be zero volts.

the nodal equation at the inverting input terminals node is −

$$\mathrm{\frac{0 \: + \: v_{r}b_{2}}{2^{0}r} \: + \: \frac{0 \: + \: v_{r}b_{1}}{2^{1}r} \: + \: \frac{0 \: + \: v_{r}b_{0}}{2^{2}r} \: + \: \frac{0 \: - \: v_{0}}{r_{f}} \: = \: 0}$$

$$\mathrm{\rightarrow \: \frac{v_{0}}{r_{f}} \: = \: \frac{v_{r}b_{2}}{2^{0}r} \: + \: \frac{v_{r}b_{1}}{2^{1}r} \: + \: \frac{v_{r}b_{0}}{2^{2}r}}$$

$$\mathrm{\rightarrow \: v_{0} \: = \: \frac{v_{r}r_{f}}{r}(\frac{b_{2}}{2^{0}} \: + \: \frac{b_{1}}{2^{1}} \: + \: \frac{b_{0}}{2^{2}})}$$

substituting, r = 2r_f in the above equation,

$$\mathrm{v_{0} \: = \: \frac{v_{r}r_{f}}{2r_{f}}(\frac{b_{2}}{2^{0}} \: + \: \frac{b_{1}}{2^{1}} \: + \: \frac{b_{0}}{2^{2}})}$$

$$\mathrm{\therefore \: v_{0} \: = \: \frac{v_{r}}{2}(\frac{b_{2}}{2^{0}} \: + \: \frac{b_{1}}{2^{1}} \: + \: \frac{b_{0}}{2^{2}})}$$

the above equation represents the output voltage equation of a 3-bit binary weighted resistor dac. since the number of bits are three in the binary (digital) input, we will get seven possible values of output voltage by varying the binary input from 000 to 111 for a fixed reference voltage, v_r.

we can write the generalized output voltage equation of an n-bit binary weighted resistor dac as shown below based on the output voltage equation of a 3-bit binary weighted resistor dac.

$$\mathrm{\therefore \: v_{0} \: = \: \frac{v_{r}}{2}(\frac{b_{n-1}}{2^{0}} \: + \: \frac{b_{n-2}}{2^{1}} \: + \dotso \: + \: \frac{b_{0}}{2^{n-1}})}$$

disadvantages of weighted resistor dac

the disadvantages of the binary weighted resistor dac are as follows −

the difference between the resistance values corresponding to lsb & msb will increase as the number of bits present in the digital input increases.
it is difficult to design more accurate resistors as the number of bits present in the digital input increases.

r-2r ladder dac

the r-2r ladder dac overcomes the disadvantages of a binary weighted resistor dac. as the name suggests, r-2r ladder dac produces an analog output, which is almost equal to the digital (binary) input by using a r-2r ladder network in the inverting adder circuit.

the circuit diagram of a 3-bit r-2r ladder dac is shown in the following figure −

the digital switches shown in the above figure will be connected to ground, when the corresponding input bits are equal to '0'. similarly, the digital switches shown in above figure will be connected to the negative reference voltage, v_r when the corresponding input bits are equal to '1'.

it is difficult to get the generalized output voltage equation of a r-2r ladder dac. but we can find the analog output voltage values of r-2r ladder dac for individual binary input combinations easily.

advantages of r-2r ladder dac

the advantages of a r-2r ladder dac are as follows −

r-2r ladder dac contains only two values of resistor: r and 2r. so, it is easy to select and design more accurate resistors.
if a greater number of bits are present in the digital input, then we have to include required number of r-2r sections additionally.

due to the above advantages, r-2r ladder dac is preferable over binary weighted resistor dac.

important parameters of dacs

the following are some key parameters and factors that we must consider while selecting a digital to analog converter for a specific application −

resolution

the number of discrete output levels that a digital to analog converter can produce is known as its resolution. to obtain a smoother and accurate analog output signal, the resolution of the digital to analog converter must be significantly high. the resolution of a dac is typically measured in bits.

let us understand the importance of resolution of dac. consider a dac that can handle 8-bits, it can represent 2⁸ = 256 discrete output values. on the other hand, if a dac can handle 16-bits, then it is able to represent 2¹⁶ = 65536 discrete output values. hence, the dac with 16-bits can provide a smoother and more accurate representation of the digital signal in analog format as compared to that the 8-bit dac can do.

accuracy

the accuracy of a digital to analog converter is the measure of how closer is the output analog signal to the input digital signal. the high accuracy of dac is an essential factor to produce a highly precise analog output signal.

power consumption

this factor provides information about the power consumed by the digital to analog converter during its operation. ideally, a digital to analog converter must be power efficient, so that it can extend the battery life and minimize the operational cost.

operating speed

the operating speed of a digital to analog converter represents the rate at which the dac converts a digital signal into analog signal. typically, the speed of a dac is measured in samples per second (s/s) or megahertz (mhz).

the operating speed of the digital to analog converter also determines the maximum frequency of the analog output signal that the dac can generate accurately.

it is essential that a digital to analog converter used in applications like real-time signal processing, generation of fast waveforms, high-speed communication, etc. must have a significantly high-speed.

noise performance

the noise performance of a digital to analog converter represents the amount of noise that can be introduced in the output signal during the conversion process. the unwanted noise can affect the signal-to-noise ratio and hence the signal quality. therefore, we should minimize the noise as much as possible to obtain a high-quality output analog signal.

applications of digital to analog converters

digital to analog converters are widely used in a variety of applications in the field of digital electronics. the main function of a digital to analog converter is to convert a digital signal into analog format.

the following are some common devices and systems in which the digital to analog converters are used −

audio amplifiers and playback systems
video encoder systems
data acquisition systems
calibration of testing and measuring instruments
motor control circuits
digital signal processors
telecommunication systems, etc.

conclusion

digital to analog converters are used in the field of electronics to provide an interface between digital input and analog output. in this chapter, we explained in detail about the types and applications of analog to digital converters.

a digital to analog converter is an electronic device that converters a digital signal into analog format. on the other hand, an analog to digital converter is an electronic device that converters an analog signal into digital format. both dac (digital to analog converter) and adc (analog to digital converter) play an important role in different fields of electronic such as communication, signal processing, computing technologies, control and automation systems, and more.

with the advancement of technology, we can design and implement the analog to digital converters and digital to analog converters in the form of ic or integrated circuits. this chapter is meant for explaining some important adc and dac ics commonly used in electronic circuits and systems.

what are dac and adc ics?

dac and adc ics are small electronic devices and integrated circuits used in the field of electronics to convert a digital signal into analog format and analog signal into digital format respectively.

the adc ic (analog to digital converter ic) is used to convert analog signals into digital format. these ics take the analog signals as input and sample them at regular intervals of time. then, they produce digital representation of the analog input signal as output.

there is another type of ic called dac ic (digital to analog converter ic) that is used to convert digital signals into analog format. hence, the dac ics take digital signals as input and produce their analog representation as output.

the adc and dac ics are important components in several different types of electronic systems where converting signals between the analog and digital formats are crucial.

popular dac and adc ics

the following are some commonly used dac and adc ics that are widely used in various electronic applications −

adc 0809 (8-bit adc ic)
icl 7109 (12-bit binary adc ic)
dac 0808 (8-bit dac ic)

let us discuss about these adc and dac ics in detail along with their features and applications.

adc 0809 ic

the adc 0809 ic is an analog to digital converter ic. it is a monolithic cmos device that consists of an 8-bit analog to digital converter, an 8-bit multiplexer, and a microprocess compatible control unit.

the adc 0809 ic uses successive approximation technique to perform analog to digital conversion. it comes in a 28-pin molded ic carrier package. the pin diagram of the adc 0809 ic is shown in the following figure.

this ic is one of the widely used adc ics in various digital electronics and microcontroller-based circuits and systems to convert analog signals into their digital format.

features of adc 0809 ic

some of the key features of adc 0809 ic are listed below −

the adc 0809 ic is an 8-bit analog to digital converter ic. hence, it can represent an analog input signal with a resolution of 8 bits or 2⁸ = 256 possible discrete values in digital format.
the adc 0809 ic provides an easy interfacing with all microprocessors.
it does not require the external zero or full-scale adjustments.
it also consists an 8-channel single ended analog signal multiplexer.
it can operate ratiometrically or with a 5 v dc voltage or an analog span adjusted voltage reference.
the output of the adc 0809 ic meets the ttl voltage level requirements.
the adc 0809 ic can operate with low power consumption, typically 15 mw that makes making it best suited for batterypowered devices.
it can support 0 v to 5v input analog voltage range with a single supply of 5 v dc.
it has a conversion time of around 100 s.

applications of adc 0809 ic

the adc 0809 ic is an ideal device in various applications such as automation, process and machine control, consumer electronics, automotives, etc. some common applications of this adc ic are listed here −

the adc 0809 ic is most commonly used in data acquisition systems to convert analog input signals received from sensors, transducers, and other analog measuring devices into digital format to process and analyze them using digital systems.
the adc 0809 ic is also used in different applications in the field of instrumentation and control engineering. it is mainly employed for precise measurement and monitoring of analog signals like temperature, pressure, and motor control.
in the field of industrial automation, the adc 0809 ic is used for digitalization of analog process and control signals which are then used for automation and monitoring of control and manufacturing processes.
the adc 0809 ic is also used in various consumer electronic devices such as digital multimeters, audio and music systems, etc. for providing an interface between analog signals and digital circuits.

icl 7109 ic

the icl 7109 ic is a monolithic 12-bit analog to digital converter (adc) ic primarily designed for easy interfacing with microprocessor-based systems and universal asynchronous receiver-transmitter (uart).

the icl 7109 ic comes in a 40-pin ic package whose pin configuration diagram is shown in the following figure −

features of icl 7109 ic

some of the key features of the icl 7109 adc ic are described below −

the icl 7109 ic is a 12-bit dual slope integrating analog to digital converter ic. hence, it provides a resolution of 12-bits that enables it to represent the analog input signals with a higher precision in digital format.
the icl 7109 ic provides an easy interfacing with microprocessors. this feature makes it ideally suitable for applications where analog signals are required to be processed or analyzed using digital systems like computers.
the icl 7109 ic also provides facility of interfacing with uart (universal asynchronous receiver/transmitter) systems. this feature allows for serial data transmission and communication with external digital devices. it also has some control lines like run/(hold) inputs and status output that can be used to monitor and control the conversion timing.
the icl 7109 ic does not require any special handling precautions because its all inputs are fully protected against static discharge.
the icl 7109 ic provides true differential input and differential reference. it provides low noise and high accuracy.
the icl 7109 ic offers a low drift typically less than 1 v/c. this ensures high precision in analog to digital conversion under varying environmental conditions.
the icl 7109 ic consumes les power that makes it ideally suitable for battery powered devices.

applications of icl 7109 ic

the icl 7109 ic is one of the commonly used analog to digital converter ic in various digital and microprocessor based systems. here are some common examples of applications of the icl 7109 ic −

the icl 7109 ic is commonly used in digital systems where accurate and high-performance conversion of analog signals into digital format is needed. it widely used in industrial monitoring, instrumentation, and scientific measurement systems.
since the icl 7109 ic is compatible with universal asynchronous receiver/transmitter (uart) systems. hence, it is used for interfacing between industry standard uarts for transmission of digital data serially over communication channels.
in industrial automation and control systems, the icl 7109 ic is employed for converting analog process and control signals into digital data for processing and controlling by microprocessors and microcontrollers.
due to high accuracy and low power consumption, the icl 7109 ic is best suited to utilize in battery powered testing and measuring instruments, where precise measurement of analog signals is desired.
the icl 7109 ic is also used in numerous consumer electronic devices for converting analog signals into digital format accurately, which is crucial for proper functioning of the device.

dac 0808 ic

the dac 0808 ic is an 8-bit digital to analog converter ic designed to convert a digital input signal into its analog representation. it is a monolithic ic known for its high accuracy and low power consumption in digital to analog conversion process.

this ic comes in the dual-in-line ic package with 16 pins. the following depicts the pin diagram of the dac 0808 ic.

due to its features like high accuracy, low power consumption, and fast settling time, it is commonly used in microcontroller-based and other digital electronic systems.

features of dac 0808 ic

the following are the key features of dac 0808 ic, making it best suited to use in digital systems −

the dac 0808 ic has a resolution of 8-bits. hence, it can convert a digital input signal into the analog format precisely. it provides high accuracy in digital to analog conversion. typically, it can convert a digital signal into analog format with a maximum error of around $\mathrm{\pm 0.9 \%}$.
the dac 0808 ic produces a full-scale current match, typically $\mathrm{\pm 1}$ lsb. this feature helps maintain the relative accuracy in the output current.
the dac 0808 ic has a fast-settling time typically 150 ns. thus, this ic can adjust its output to match the desired analog voltage in a very short time.
the dac 0808 ic is compatible with both ttl and cmos devices.
the dac 0808 ic has a high-speed multiplying input slew rate. therefore, it can change its output voltage at a very fast speed when the digital input to it changes. typically, the slew rate of the dac 0808 ic is 8 ma/s.
the dac 0808 ic can operate with a power supply voltage range varying from $\mathrm{\pm 4.5}$ v to $\mathrm{\pm 18}$ v. this feature makes it versatile to use in systems operating at different voltage levels.
the dac 0808 ic consumes very low power. typically, it consumes only 33 mw of power at an operating voltage of $\mathrm{\pm 5}$ v. this feature makes it suitable to use in battery power devices where energy efficiency is critical.

applications of dac 0808 ic

the dac 0808 ic is widely used in a variety of applications across different fields such as audio signal processing, industrial automation, and control systems for the conversion of digital signals into analog voltages. some key examples illustrating the applications of the dac 0808 ic are given below −

the dac 0808 ic is very commonly used in waveform generators to produce analog output voltages from digital input data. it allows us to produce various types of waveforms like sine waves, square waves, triangular waves, etc.
in the field of instrumentation and control, the dac 0808 ic is employed for producing analog signals that can be used in calibration, simulation, and testing applications.
the dac 0808 ic is also used in motor control circuits to produce analog voltage signals from digital inputs. these analog output signals are then used for operating motor drives, actuators, and servo systems.
the dac 0808 ic is also used in various audio systems such as audio playback systems, synthesizers, musical instruments, audio effects processors, etc. to perform digital to analog conversion.
in industrial automation and control systems, the dac 0808 ic is utilized to produce analog signals used to control and regulate the processes, operate the valves, and adjust the system variables based on digital inputs provided by microcontrollers or plcs.

conclusion

there are several different adc and dac ics available in the market and are used depending on the specific requirements of the application. in this chapter, we explained the pin diagram, key features, and applications of some popular types of dac and adc ics.

in conclusion, a dac ic is a digital to analog converter chip that can convert digital input signals into analog output voltages at a very high speed and efficiency. on the other hand, an adc ic is an analog to digital converter chip that converts analog input signals into digital output signals. these ics are so designed that they are compatible with various digital systems and low power devices.

before getting into implementing a not gate using nand gate, lets have a basic overview of not gates and nand gates.

what is not gate?

not gate is a basic logic gate used in digital electronic circuits. the not gate has a single input and a single output. the output of the not gate is the logical inversion of its input. for this reason, the not gate is also known as inverter.

implementation of not gate using nand gate 1

the symbol of the standard not gate has a triangle pointing to the right with a circle at its right end as shown in figure-1. this circle is referred to as an inversion bubble. the not gate produces an output which is the complement or inversion of its input. for example, if we give a high input single, then it provides a low output signal. similarly, when we give a low input signal, then it provides a high output signal.

since, the not gate is a single input device, therefore, it is not used as a decision making component in the logic circuits.

truth table of not gate

the following is the truth table of not gate −

input (a)	output (y = a)
0	1
1	0

boolean expression of not gate

the following is the boolean expression of the not gate −

$$\mathrm{y \: = \: a'}$$

for a not gate, if a is 1 (high / true), then y is 0 (low / false), and vice-versa.

what is nand gate?

nand is a universal logic gate. it is a digital logic gate having two or more input terminals and gives an output depending on the combination of the input signals. nand represents not + and, i.e. it produces an output which is the inversion or compliment of logic and operation.

since, nand is a universal logic gate, therefore, it can be used to implement all kinds of logic operations like or, and, not. the symbol of the nand gate is shown in figure-2.

implementation of not gate using nand gate 2

from the symbol, it is clear that it has a shape of standard and gate with a circle. this circle is known as inversion bubble. the symbol gives the idea about the operation of the nand gate, i.e. it takes inputs, performs and operations, and at last takes the inversion of the result of and operation to provide the final output of the nand gate.

truth table of nand gate

the following is the truth table of the nand gate −

inputs		output
a	b	y = (ab)
0	0	1
0	1	1
1	0	1
1	1	0

from the truth table of nand gate, it is clear that the operation of the nand gate is same as that of the and gate followed by a not gate. for this reason, the symbol of the nand is like as shown in the figure-2.

boolean expression of nand gate

the following is the boolean expression of the nand gate −

$$\mathrm{y \: = \: (ab)'}$$

now, let us discuss the implementation of not gate using nand gate.

implementation of not gate using nand gate

as we discussed in the above section that the nand gate is a universal gate, thus we can use it to realize any basic logic gate. the realization of not gate using nand gate is shown in figure-3.

from figure-3, it is clear that to realize the not gate using the nand gate, we have to join the two input terminals of the nand gate to form a single input terminal of the not gate, and the output of the not gate is taken from the output terminal of the nand gate.

truth table of not gate using nand gate

the following is the truth table of not gate using nand gate −

inputs		output
a	b	y = (ab) = a
0	0	1
1	1	0

hence, this is all about the implementation of not gate using nand gate.

nand gate is a universal logic gate, using which we can realize any logic gate. read this tutorial to find out how you can realize an or gate using a nand gate. before going into the implementation part, let's have a brief overview of or and nand gates.

what is an or gate?

an or gate is a basic logic gate. an or gate may accept two or more than two inputs, but gives only one output. the or gate gives a high (logic 1) output if any one of its inputs is in the high or logic 1 state, otherwise, it gives a low (logic 0) state as output. therefore, the output of the or gate is low or logic 0 state, only if its all inputs are low or logic 0 state.

the or gate is also known as an "any or all gate" or "an inclusive or gate". the logic symbol of a two input or gate is shown in figure-1.

implementation of or gate from nand gate 1

output equation of or gate

if a and b are the input variables and y is the output variable, then the output equation of the or gate is given by,

$$\mathrm{y \: = \: a \: + \: b}$$

where, the '+' symbol represents the or operation. it is read as y is equal to a or b.

truth table of or gate

the table that shows the relationship between inputs and output of a logic gate is referred to as a truth table. the following is the truth table for the or gate −

input		output
a	b	y = a + b
0	0	0
0	1	1
1	0	1
1	1	1

what is a nand gate?

the nand gate is a type of universal logic gate. where, a universal logic gate is one that can be used to realize any kind logical expression or any other type of logic gate.

a nand gate is basically a combination of two basic logic gates namely and gate and not gate, i.e.,

$$\mathrm{nand \: logic \: = \: and \: logic \: + \: not \: logic}$$

a nand gate is the type of logic gate whose output is low (logic 0) when all its inputs are high, and its output is high (logic 1), when any of its inputs is low (logic 0). therefore, the operation of the nand gate is opposite that of the and gate. the logic symbol of a two input nand gate is shown in figure-2.

implementation of or gate from nand gate 2

output equation of nand gate

if a and b are the input variables and y is the output variable of the nand gate, then its output is given by,

$$\mathrm{y \: = \: \overline{a \: \cdot \: b} \: = \: (a \: \cdot \: b)'}$$

it is read as "y is equal to a.b whole bar".

truth table of nand gate

the following is the truth table of the nand gate −

input		output
a	b	y = (a·b)'
0	0	1
0	1	1
1	0	1
1	1	0

now, let us discuss the implementation of or gate from nand gate.

implementation of or gate from nand gate

the nand gate is a universal gate, therefore, it can be used to realize the or gate. the implementation of or gate using the nand gate is shown in figure-3.

the nand circuit shown in figure-3 is equivalent to an or gate. it is also known as bubbled nand gate, where the bubbled nand gate is equivalent to the or gate in operation.

theory of or gate using nand gate

to realize the or gate using nand gate, we first complement the inputs a and b. this is done by the nand gate 1 and 2 in the above figure-3. then, these complemented inputs, i.e. a' and b' are applied to a nand gate (nand gate 3). thus, we get,

$$\mathrm{y \: = \: \overline{\bar{a} \: \cdot \: \bar{b}}}$$

using de morgen's law, we have,

$$\mathrm{y \: = \: \bar{\bar{a}} \: + \: \bar{\bar{b}} \: = \: a \: + \: b}$$

this is the output equation of the or gate. therefore, the logic circuit of nand gates in figure-3 is equivalent to the or gate.

as we know that the nand gate is a universal logic gate, therefore using the nand gate, we can implement any logic gate or any other logical expression. read this tutorial to understand how you can implement an and gate using nand gate. let's start with a basic overview of and and nand gates.

what is an and gate?

an and gate is a basic logic gate. an and gate may have two or more than two inputs, but gives only one output. the and gate gives a low (logic 0) output if any one of its inputs is in the low or logic 0 state, otherwise, it gives a high (logic 1) state as output. therefore, the output of the and gate is high or logic 1 state, only if all its inputs are high or logic 1 state.

the and gate is also known as an "all or nothing gate". the logic symbol of a two input and gate is shown in figure-1.

implementation of and gate from nand gate 1

output equation of and gate

if a and b are the input variables and y is the output variable for an and gate, then the output equation of the and gate is given by,

$$\mathrm{y \: = \: a\cdot b}$$

where, the "·" (dot) symbol represents the and operation. it is read as y is equal to a and b.

truth table of and gate

the table that show the relationship between inputs and output of a logic gate is referred to as a truth table. the following is the truth table for the and gate −

input		output
a	b	y = a · b
0	0	0
0	1	0
1	0	0
1	1	1

what is a nand gate?

the nand gate is a type of universal logic gate. where, a universal logic gate is one that can be used to realize any kind logical expression or any other type of logic gate.

a nand gate is basically a combination of two basic logic gates namely and gate and not gate, i.e.

$$\mathrm{nand \: logic \: = \: and \: logic \: + \: not \: logic}$$

implementation of and gate from nand gate 2

output equation of nand gate

if a and b are the input variables and y is the output variable of the nand gate, then its output is given by,

$$\mathrm{y | \: = \: \overline{a \: \cdot \: b} \: = \: (\arrowvert a \: \cdot \: b)'}$$

it is read as "y is equal to a·b whole bar".

truth table of nand gate

the following is the truth table of the nand gate −

input		output
a	b	y = (a · b)'
0	0	1
0	1	1
1	0	1
1	1	0

now, let us discuss the implementation of and gate from nand gate.

implementation of and gate from nand gate

as discussed above that the nand gate is a type of universal logic gate, because it can be used to implement any other logic gate. the implementation of an and gate using nand gate is shown in figure-3.

from this circuit diagram, it is clear that the implementation of the and gate from nand gate is quite simple, as we just require two nand gates.

where, the first nand gate produce a complement binary product of inputs a and b, while the second nand gate again complement the output of first nand gate to produce an and output. therefore, the logic circuit using nand gates shown in figure-3 is equivalent to the and gate.

output equation

the output produced by the first nand gate is,

$$\mathrm{y_{1} \: = \: \overline{a \: \cdot \: b}}$$

the output produced by the second nand gate is,

$$\mathrm{y \: = \: \overline{\overline{a \: \cdot \: b}} \: = \: a \: \cdot \: b}$$

this is the output equation of the and gate.

nor and nand gates are universal logic gates, using which we can implement any logic gate or any other logical expression. read this tutorial to find out how you can implement a nor gate using a nand gate.

what is a nor gate?

nor gate is a type of universal logic gate, because this logic gate can be used for implementation of any other type of logic gate.

nor means "not + or". that means the or output is noted or inverted. therefore, the nor gate is a combination of or gate and a not gate.

$$\mathrm{nor \: gate \: = \: or \: gate \:+ \: not \: gate}$$

a nor gate is a type of logic gate whose output is high (logic 1), only when all its inputs are low (logic 0), and it gives an output low (logic 0), even if any of its inputs become high (logic 1). the logic symbol of a two input nor gate is shown in figure-1.

implementation of nor gate from nand gate 1

output equation of nor gate

if a and b are the input variables and y is the output variable of the nor gate, then the output of the nor gate is given by,

$$\mathrm{y \: = \: \overline{a \: + \: b} \: = \: (a \: + \: b)'}$$

it is read as "y is equal to a plus b whole bar".

truth table of nor gate

the table that shows the relationship between inputs and output of a logic gate is referred to as a truth table. the following is the truth table of the nor gate −

input		output
a	b	y = (a + b)'
0	0	1
0	1	0
1	0	0
1	1	0

what is a nand gate?

the nand gate is a type of universal logic gate. where, a universal logic gate is one that can be used to realize any kind logical expression or any other type of logic gate.

a nand gate is basically a combination of two basic logic gates namely and gate and not gate, i.e.,

$$\mathrm{nand \: logic \: = \: and \: logic \: = \: not \: logic}$$

implementation of nor gate from nand gate 2

output equation of nand gate

if a and b are the input variables and y is the output variable of the nand gate, then its output is given by,

$$\mathrm{y \: = \: \overline{a \: \cdot \: b} \: = \: (a \: + \: b)'}$$

it is read as "y is equal to a.b whole bar".

truth table of nand gate

the following is the truth table of the nand gate −

input		output
a	b	y = (a·b)'
0	0	1
0	1	1
1	0	1
1	1	0

now, let us discuss the implementation of nor gate from nand gate.

implementation of nor gate from nand gate

as mentioned above, the nand gate is a universal logic gate, therefore, it can be used to realize the any other logic gate. the implementation of nor gate using the nand gate is shown in figure-3.

from the logic circuit, it is clear that for the implementation of nor gate using nand gates only, we require 4 nand gates. the first two nand gates perform the complement of input variables a and b, the third nand gate produce the nand output of the complemented inputs, i.e. a' and b'. finally, the fourth nand gate again operates as an inverter and produce the output y. this output y is the equivalent to the output of the nor gate.

output equation

the output of the first and second nand gates is,

$$\mathrm{y_{1} \: = \: \bar{a} \:\: and \:\: y_{2} \: = \: \bar{b}}$$

the output of the third nand gates is,

$$\mathrm{y_{3} \: = \: \overline{\bar{a} \: \cdot \: \bar{b}} \: = \: a \: + \: b}$$

the output of the fourth nand gate is,

$$\mathrm{y \: = \: \overline{a \: + \: b}}$$

hence, this is the output of a nor gate. in this way, we can implement a nor gate using nand gates only.

the nand gate is a universal logic gate, using which we can implement any other type of logic gate or logical expression. read this tutorial to understand how you can implement a xor gate using only nand gates. let's start with a basic overview of xor and nand gates

what is a xor gate?

the xor (exclusive-or) gate is a type of derived logic gate. the xor gate is a logic gate that has two inputs and one output. the xor gate produces a high (logic 1) output when one and only one of its two inputs are high (logic 1). when both inputs of the xor gate are high (logic 1) or low (logic 0), then the output of the xor gate is a low (logic 0) state. the logic symbol of the xor gate a is shown in figure-1.

implementation of xor gate from nand gate 1

hence, the xor gate produces an output high only when its inputs are not equal. therefore, the xor gate is also known as "anti-coincidence gate" or "inequality detector".

output equation of xor gate

the output of the xor gate is the modulo sum of its inputs, i.e.,

$$\mathrm{y \: = \: a \oplus b \: = \: a \: \bar{b} \: + \: \bar{a} \: b}$$

where, a and b are the two input variables to the xor gate, y is the output variable of the xor gate. the output expression of the xor gate is read as y is equal to a ex-or b.

truth table of xor gate

the truth table shows the relationship between inputs and output of the xor gate. the truth table of an xor gate is shown below.

input		output
a	b	y = (ab' + a'b)
0	0	0
0	1	1
1	0	1
1	1	0

what is a nand gate?

a nand gate is a type of universal logic gate that can be used to realize any kind logical expression or any other type of logic gate. a nand gate is basically a combination of two basic logic gates namely, and gate and not gate, i.e.,

$$\mathrm{nand \: logic \: = \: and \: logic \: = \: not \: logic}$$

implementation of xor gate from nand gate 2

output equation of nand gate

if a and b are the input variables and y is the output variable of the nand gate, then its output is given by

$$\mathrm{y \: = \: \overline{a \cdot b} \: = \: (a \cdot b)'}$$

it is read as "y is equal to a·b whole bar".

truth table of nand gate

the following is the truth table of the nand gate −

input		output
a	b	y = (a.b)'
0	0	1
0	1	1
1	0	1
1	1	0

now, let us discuss the implementation of xor gate from nand gate.

implementation of xor gate from nand gate

as discussed above, the nand gate is a universal logic, hence, using which we may implement any other logic gate. figure-3 shows how you can implement a xor gate using only nand gates.

from the logic circuit diagram of the xor gate using nand gates only, it is clear that we require 4 nand gates.

now, let us understand how this nand logic circuit functions to produce an output equivalent to the xor gate.

the output of the first nand gate is,

$$\mathrm{y_{1} \: = \: \overline{a \: b}}$$

the outputs of the secondary and third nand gates are,

$$\mathrm{y_{2} \: = \: \overline{a \cdot \overline{ab}}}$$

$$\mathrm{y_{3} \: = \: \overline{b \cdot \overline{ab}}}$$

finally, these two outputs (y2 and y3) are connected to the fourth nand gate. this nand gate will produce an output which is,

$$\mathrm{y \: = \: \overline{\overline{a \cdot \overline{ab}} \cdot \overline{b \cdot \overline{ab}}}}$$

$$\mathrm{\rightarrow \: y \: = \: a \cdot \overline{ab} \: + \: b \cdot \overline{ab} \: = \: a(\bar{a} \: + \: \bar{b}) \: + \: b(\bar{a} \: + \: \bar{b})}$$

$$\mathrm{\rightarrow \: y \: = \: a \: \bar{a} \: + \: a \: \bar{b} \: + \: \bar{a} \: b \: + \: b \: \bar{b}}$$

$$\mathrm{\therefore \: y \: = \: a \: \bar{b} \: + \: \bar{a} \: b \: = \: a \oplus b}$$

this is the output of the xor gate. hence, in this way, we can implement the xor gate from nand gates only.

as we know, the nand gate is a universal logic gate, using which we can implement any other type of logic gate or logical expression. read this tutorial to find out how you can implement an xnor gate using only nand gates. let's start with a basic overview of xnor and nand gates.

what is an xnor gate?

the xnor (exclusive-nor) gate is a type of derived logic gate. the xnor gate is a logic gate that has two inputs and one output. the xnor gate produces a high (logic 1) output when both of its inputs are equal, i.e. either high (logic 1) or low (logic 0).

when the inputs of the xnor gate are different, i.e., one is high (logic 1) and another is low (logic 0), then the output of the xnor gate is a low (logic 0) state. the logic symbol of the xnor gate is shown in figure-1.

implementation of xnor gate from nand gate 1

hence, the xnor gate produces an output high (logic 1) only when both of its inputs are equal. thus, the xnor gate is also known as "equality detector".

the output of the xnor gate is given by,

$$\mathrm{y \: = \: a \odot b \: = \: ab \: + \: \bar{a} \: \bar{b}}$$

where, a and b are the two input variables to the xnor gate, y is the output variable of the xnor gate. the output expression of the xnor gate is read as y is equal to a ex-nor b.

truth table of xnor gate

the truth table shows the relationship between inputs and output of the xnor gate. the truth table of an xnor gate is shown below.

input		output
a	b	y = (ab + a'b')
0	0	1
0	1	0
1	0	0
1	1	1

what is a nand gate?

the nand gate is a type of universal logic gate. where, a universal logic gate is one that can be used to realize any kind logical expression or any other type of logic gate.

a nand gate is basically a combination of two basic logic gates namely and gate and not gate, i.e.,

$$\mathrm{nand \: logic \: = \: and \:logic \: + \: not \: logic}$$

implementation of xnor gate from nand gate 2

output equation of nand gate

if a and b are the input variables and y is the output variable of the nand gate, then its output is given by,

$$\mathrm{y \: = \: \overline{a \cdot b} \: = \: (a \cdot b)'}$$

it is read as "y is equal to a·b whole bar".

truth table of nand gate

the following is the truth table of the nand gate −

input		output
a	b	y = (a·b)'
0	0	1
0	1	1
1	0	1
1	1	0

now, let us discuss the implementation of xnor gate from nand gate.

implementation of xnor gate from nand gate

as discussed above, the nand gate is a universal logic, using which we can implement any other type of logic gate. the realization of xnor gate using nand gates is shown in figure-3.

from the logic circuit diagram of the xnor gate using nand gates only, it is clear that we require 5 nand gates.

now, let us understand how this nand logic circuit functions to produce an output equivalent to the xnor gate −

the output of the first nand gate is,

$$\mathrm{y_{1} \: = \: \overline{a \: b}}$$

the outputs of the secondary and third nand gates are,

$$\mathrm{y_{2} \: = \: \overline{a \cdot \: \overline{ab}}}$$

$$\mathrm{y_{3} \: = \: \overline{b \cdot \: \overline{ab}}}$$

these two outputs (y2 and y3) are connected to the fourth nand gate. this nand gate will produce an output which is,

$$\mathrm{y \: = \: \overline{\overline{a \cdot \: \overline{ab}} \cdot \overline{b \cdot \overline{ab}}}}$$

$$\mathrm{\rightarrow \: y \: = \: a \cdot \overline{ab} \: + \: b \cdot \overline{ab} \: = \: a(\bar{a} \: + \: \bar{b}) \: + \: b(\bar{a} \: + \: \bar{b})}$$

$$\mathrm{\rightarrow \: y \: = \: a \: \bar{a} \: + \: a \: \bar{b} \: + \: \bar{a} \: b \: + \: b \: \bar{b}}$$

$$\mathrm{\therefore \: y \: = \: a \: \bar{b} \: + \: \bar{a} \:b \: = \: a \oplus b}$$

finally, the output of the fourth nand gate is input to the fifth nand gate that functions as an inverter, and produces an output equivalent to the xnor gate, i.e.,

$$\mathrm{y \: = \: \overline{a \oplus b} \: = \: a \odot b}$$

this is the output of the xnor gate. therefore, in this way, we can implement the xnor gate from nand gates only.

a not gate is a basic logic gate that gives an output which is complement of its input. a nor gate is a universal logic gate that can be used to implement any other type of logic gate. a nor gate is basically an or gate followed by a not gate.

read this tutorial to find out how you can implement a not gate using nor gate. let's start the discussion with a brief overview of not and nor gates.

what is a not gate?

in digital electronics, a not gate is a basic logic gate that has only one input and one output. it is type of logic gate whose output is always the complement of its input. therefore, the not gate is also known as an inverter.

if the input of the not gate is low (logic 0), then it gives an output that is high (logic 1). if the input is high (logic 1), then the not gate gives the low (logic 0) output. the logic symbol of the not gate is shown in figure-1.

implementation of not gate from nor gate 1

the not operation is represented by the '-' (bar) symbol. therefore, if the input variable of the not gate is a, then its output y is given by,

$$\mathrm{y \: = \: \bar{a} \: = \: a' }$$

truth table of not gate

the truth table of the not gate gives the relationship between its input variable and output variable. the following is truth table of the not gate −

input (a)	output (y = a')
a	b
0	1
1	0

what is a nor gate?

nor gate is a type of universal gate, therefore, it can be used to implement any other type of logic gate. nor gate is basically a combination of not gate and or gate, i.e. or gate followed by a not gate is a nor gate. thus,

$$\mathrm{nor \: gate \: = \: or \: gate \: = \: not \: gate}$$

a nor gate can accept any number of inputs and gives a single output. the output of the nor gate is assumed high or logic 1, only when all of its inputs are low or logic 0. for any other combination of inputs, the output of the nor gate is assumed low or logic 0. the logic symbol of a two input nor gate is shown in figure-2.

implementation of not gate from nor gate 2

the operation of the nor gate is expressed by,

$$\mathrm{y \: = \: \overline{a \: + \: b} \: = \: (a \: + \: b)'}$$

where, a and b are the input variables and y is the output variable of the nor gate. the output expression of the nor gate is read as "y is equal to a plus b whole bar".

truth table of nor gate

for different combinations of inputs, we can analyze the operation of the nor gate using its truth table, which is given below.

input		output
a	b	y = (a + b)'
0	0	1
0	1	0
1	0	0
1	1	0

now, let us discuss the implementation of not gate using nor gate.

implementation of not gate from nor gate

as discussed above, a nor gate is a universal gate, therefore, we can use it to realize any other type of logic gate. the implementation of not gate from nor gate is shown in figure-3.

hence, to realize the not gate using nor gate, we simply join all its inputs terminals together and apply the signal to be noted or inverted to this common input terminal.

also, we can use the nor gate as a not gate by connecting all its input terminals except one to logic 0, and applying the signal to be inverted to the remaining terminal. this configuration of nor gate as not gate is referred to as a controlled inverter.

hence, in this way, the not gate can be implemented using a nor gate only.

an or gate is a basic logic gate that gives a high or logic 1 output, when any of its inputs is high. whereas, the nor gate is a universal logic gate, which gives a high output only when all its inputs are low or logic 0. before, going into the implementation of or gate using nor gate, let us discuss the basic theory of or gate and nor gate first.

what is an or gate?

an or gate is a basic logic gate. an or gate can have two or more than two inputs, but has only one output. the or gate gives a high (logic 1) output if any one of its inputs is in the high or logic 1 state, otherwise, it gives a low (logic 0) state as output. therefore, the output of the or gate is low or logic 0 state, only if all its inputs are low or logic 0 state.

the or gate is also known as an "any or all gate" or "an inclusive or gate". the logic symbol of a two input or gate is shown in figure-1.

implementation of or gate from nor gate 1

if variables a and b are the inputs to the or gate and y is the output variable, then the output equation of the or gate is given by,

$$\mathrm{y \: = \: a \: + \: b}$$

where, the '+' symbol represents the or operation. it is read as "y is equal to a or b".

the table that show the relationship between inputs and output of an or gate is referred to as a truth table of the or gate.

truth table of or gate

the following is the truth table for the or gate.

input		output
a	b	y = a + b
0	0	0
0	1	1
1	0	1
1	1	1

what is a nor gate?

nor gate is a universal logic gate, and hence it can be used for implementation of any other type of logic gate.

nor means not + or. that means, the or output is noted or inverted. therefore, the nor gate is a combination of or gate and a not gate, i.e.,

$$\mathrm{nor \:gate \: = \:or \: gate \: = \: not \: gate}$$

a nor gate is a type of logic gate whose output is high (logic 1), only when all its inputs are low (logic 0), and it gives an output low (logic 0), even if any of its inputs becomes high (logic 1). the logic symbol of a two input nor gate is shown in figure-2.

implementation of or gate from nor gate 2

if variables a and b are the input variables to the nor gate and y is the output variable of the nor gate, then the output of the nor gate is given by,

$$\mathrm{y \: = \: \overline{a \: + \: b} \: = \: (a \: + \: b)'}$$

it is read as "y is equal to a plus b whole bar".

truth table of nor gate

the following is the truth table of the nor gate −

input		output
a	b	y = (a + b)'
0	0	1
0	1	0
1	0	0
1	1	0

now, let us discuss the implementation of or gate from nor gate.

implementation of or gate from nor gate

as we know, the nor gate is a type of universal logic gate, therefore, using nor gates only, we can implement the or operation. the logic diagram of or gate using nor gate is shown in figure-3.

hence, from the logic circuit, it is clear that we require only two nor gates for the realization of or operation.

the first nor gate performs the nor operation on variables a and b, thus the output of the first nor gate is,

$$\mathrm{y_{1} \: = \: \overline{a \: + \: b}}$$

the second nor gates perform the not operation on the output of the first nor gate. therefore, the output of the second nor gate is,

$$\mathrm{y \: = \: a \: + \: b}$$

this is the output expression of an or gate. therefore, we can realize an or gate using nor gates only as shown in figure-3.

an and gate is a basic logic gate that performs the binary multiplication, i.e., it gives a high or logic 1 output, only when all its inputs are in high or logic 1 state. on the other hand, a nor gate is a type of universal logic gate. therefore, nor gate can be used to realize any other type of logic gate.

before going into the implementation of and gate using nor gates only, let us discuss the basic theory of and gate and nor gate first.

what is an and gate?

the and gate is also known as an "all or nothing gate". the logic symbol of a two input and gate is shown in figure-1.

implementation of and gate from nor gate 1

if variables a and b are inputs to the and gate and y is the output variable of the and gate, then the output equation of the and gate is given by,

$$\mathrm{y \: = \: a\cdot b}$$

where, the '.' (dot) symbol represents the and operation. it is read as "y is equal to a and b".

truth table of and gate

the table that show the relationship between inputs and output of the and gate is referred to as the truth table of and gate. the following is the truth table of the and gate −

input		output
a	b	y = a · b
0	0	0
0	1	0
1	0	0
1	1	1

what is a nor gate?

nor gate is a type of universal logic gate, because this logic gate can be used for realization of any other type of logic gate.

nor means not + or. that means, the or output is noted or inverted. therefore, the nor gate is a combination of or gate and a not gate, i.e.,

$$\mathrm{nor \: gate \: = \: or \: gate \: + \: not \: gate}$$

implementation of and gate from nor gate 2

if variables a and b are the input variables and y is the output variable of the nor gate, then the output of the nor gate is given by,

$$\mathrm{y \: = \: \overline{a \: + \: b} \: = \: (a \: + \: b)'}$$

it is read as "y is equal to a plus b whole bar".

truth table of nor gate

the following is the truth table of the nor gate −

input		output
a	b	y = a · b
0	0	1
0	1	0
1	0	0
1	1	0

now, let us discuss the implementation of and gate from nor gate.

implementation of and gate from nor gate

as mentioned above that the nor gate is a logic gate, therefore, we may use it to realize an and gate. the realization of an and gate from the nor gates only is shown figure-3.

thus, for the realization of an and gate from nor gate, we require 3 nor gates. where, the first two nor gates are used to complement the input variables a and b, and the third nor gate is used to produce an output equivalent to the and operation.

output equation

the outputs of the first two nor gates are,

$$\mathrm{y_{1} \: = \: \bar{a}}$$

$$\mathrm{y_{2} \: = \: \bar{b}}$$

the output of the third nor gate is,

$$\mathrm{y \: = \: \overline{\bar{a} \: + \: \bar{b}} \: = \: \bar{\bar{a}} \cdot \bar{\bar{b}} \: = \: a \cdot b} $$

this is the output of an and gate. hence, the logic circuit using nor gates shown in figure-3 is equivalent to the and gate.

in digital electronics, logic gates are the basic building blocks of all digital circuits that act as the switching devices in the digital circuits. therefore, a logic gate is a digital circuit used to perform several logical operations in a digital device or system. a logic gate can accept one or multiple inputs but produces only a single output. where, the output of a logic gate is determined by the combination of input signals. the operation of the logic gates is based on the boolean algebra.

these days, logic gates are being used in every digital electronic device such as smartphones, laptops, computers, memories, etc. there are many types logic gates available such as and gate, or gate, not gate, nand gate, nor gate, xor gate, xnor gate, etc.

difference between nand gate and nor gate 1

here, we will highlight all the differences between nand gate and nor gate. both the nand gate and the nor gate are universal logic gates, which means we can implement any logical expression by using the nand and nor gates only. before getting into the differences, let's start with some basics.

what is a nand gate?

a nand gate basically a combination of not gate and and gate, i.e. not + and = nand. therefore, the nand gate is a negated version of and gate.

for a nand gate, the output of the gate is high (1), when all of its inputs are low (0) or at least one input is low. if it has all the inputs low (0), then the gate's output will be high (1). hence, from the explanation, it is clear that the nand gate is an exact inverse of the and gate.

the logical or boolean expression of a two input nand gate is given by,

$$\mathrm{y \: = \: \overline{a \cdot b} \: = \: (a \cdot b)^\prime}$$

where, y is the output of the nand gate and a and b are the binary inputs.

the nand gate follows the commutative law, i.e.

$$\mathrm{(a \: \cdot \: b)^\prime \: = \: (b \: \cdot \: a)^\prime}$$

hence, from the boolean expression of the nand gate, we can see that the output of the nand gate is obtained by multiplying all the inputs and then by taking the compliment of the multiplied result.

the following is the truth table of a two input nand gate −

inputs		and	output
a	b	a·b	y = (a·b)'
0	0	0	1
0	1	0	1
1	0	0	1
1	1	1	0

nand gates are used in realizing other logic gates, making flip-flops, registers, burglar alarm circuit, freezer warning buzzer, etc.

what is a nor gate?

the nor gate is a combination of not and or gates, i.e. or + not = nor. a nor gate consists of an or gate followed by a not gate.

for the nor gate, the output of the gate is high (1), when all its inputs are low (0). in all other cases, it produces a low output. thus, the nor gate is nothing but a negated version of the or gate.

the boolean expression of a two input nor gate is given by,

$$\mathrm{y \: = \: \overline{a \: + \: b} \: = \: (a \: + \: b)^\prime}$$

where, y is the gate's output and a & b are the inputs. hence, from the boolean expression of the nor gate, it is clear that the gate's output can be obtained by the logical addition of all the inputs and then taking the complement of the result of addition.

the following is the truth table of a two input nor gate −

inputs		or	output
a	b	a+b	y = (a+b)'
0	0	0	1
0	1	1	0
1	0	1	0
1	1	1	0

the nor gate is used in the realization of several combinational and sequential digital circuits like multiplexers, multipliers, counters, etc.

difference between nand gate and nor gate

nand and nor gates are types of universal logic gates, however, there are several differences between these that are listed in the following table −

difference	nand gate	nor gate
definition	a nand gate is a universal logic gate which performs the negated logical multiplication.	a nor gate is a universal logic gate which performs the negated logical addition.
implementation	nand gate can be implemented by using an and gate followed by a not gate.	nor gate can be implemented by using an or gate followed by a not gate.
representation	the operation of nand gate can be represented by the complimented and operation, i.e. (·)'.	the operation of a nor gate can be represented by the complimented or operation, i.e. (+)'.
boolean expression	the boolean expression of a two input nand gate is given by, $\mathrm{y \: = \: \overline{a \cdot b} \: = \: (a \: \cdot \: b)^\prime}$	the boolean expression of a two input nor gate is given by, $\mathrm{y \: = \: \overline{a \: + \: b} \: = \: (a \: + \: b)^\prime}$
low output	the nand gate produces a low (0) output, when all its inputs are high.	the nor gate produces a low (0) output, when all its inputs or at least one input is high (1).
high output	the nand gate produces a high (1) output, when all its inputs or at least one input is low (0).	the nor gate produces a high (1) output, when all its inputs are low (0).
applications	the nand gate is used in constructing other logic gates, making flip-flops, registers, implementing burglar alarm circuit, freezer warning buzzer, etc.	the nor gate is used in the implementation of various combinational and sequential digital circuits like multiplexers, multipliers, counters, etc.

conclusion

the most significant difference between these two gates is that the nand gate executes a negated logical multiplication, while the nor gate executes a negated logical addition.

to carry out numerous logical processes, logic gates are crucial elements in the design of digital circuits. one such gate that generates a high output when the inputs are different from one another is the xor (exclusive or) gate. using nor gates to create an xor gate is an intriguing strategy that will be discussed in this tutorial. understanding this implementation helps us better grasp the flexibility and relationships between logic gates.

what is a xor gate?

another fundamental logic gate that is frequently utilised in digital circuits is the xor (exclusive or) gate. when there are an odd number of high inputs, it generates a high output. to put it another way, the output is only high when the inputs are different from one another.

truth table of xor gate

a two-input xor gate's truth table is as follows −

input a	input b	output
0	0	0
0	1	1
1	0	1
1	1	0

the boolean expression for a two-input xor gate is −

$$\mathrm{output \: = \: a \: \oplus \: b}$$

where '$\mathrm{\oplus}$' represents the xor operation.

nor gate

a nor gate is a type of logic gate that executes a logical disjunction (or) and then a logical negation (not). it generates a single output signal from two or more input signals. only when all of a nor gate's inputs are low (0) will the output be high (1), and for all other input configurations, the output will be low (0).

truth table of nor gate

a two-input nor gate's truth table is as follows −

input a	input b	output
0	0	1
0	1	0
1	0	0
1	1	0

the boolean expression for a two-input nor gate is −

$$\mathrm{output \: = \: \thicksim \: (a \: + \: b)}$$

where '~' represents logical negation (not) and '+' represents logical disjunction (or).

numerous more logic gates and intricate digital circuits can be implemented using nor gates, which are frequently used in digital circuits. since they are regarded as universal gates, any other logic gate or circuit can be built only out of nor gates.

implementation of xor gate from nor gate

it takes at least five nor gates to create the circuit diagram for an xor gate using only nor gates. more than five nor gates can also contain an xor gate. the schematic for an xor gate employing five nor gates is shown in the accompanying figure.

$$\mathrm{y \: = \: (a \: \overline{b} \: + \: \overline{a} \: b)}$$

here is how to obtain the output of xor gate from the above circuit −

the leftmost nor gate has inputs a and b and its output is $\mathrm{\overline{a+b}}$

inputs for the upper nor gate are a and $\mathrm{\overline{a+b}}$ and the output is $\mathrm{\overline{a \: + \: \overline{a+b}}}$

again, the inputs for the lower nor gate are b and $\mathrm{\overline{a+b}}$ and its output is $\mathrm{\overline{b \: + \: \overline{a+b}}}$

the inputs for the 4th nor gate are the outputs of the upper and lower nor gates i.e. $\mathrm{\overline{a \: + \: \overline{a+b}}}$ and $\mathrm{\overline{b \: + \: \overline{a+b}}}$

the output of the 4th nor gate = $\mathrm{\overline{\overline{a \: + \: \overline{a+b}} \: + \: \overline{b \: + \: \overline{a+b}}}}$

$\mathrm{= \: \overline{\overline{a}\cdot \: \overline{(\overline{a \: + \: b})} \: + \: \overline{b}\cdot \: \overline{(\overline{a \: + \: b})}}}$

$\mathrm{\overline{\overline{a}\cdot \: (a \: + \: b) \: + \: \overline{b}\cdot \: (a \: + \: b)}}$

$\mathrm{\overline{\overline{a}\cdot \: a \: + \: \overline{a}\cdot \: b \: + \: \overline{b}\cdot \: a \: + \: \overline{b}\cdot \: b}}$

$\mathrm{\overline{\overline{a}\cdot \: b \: + \: \overline{b}\cdot \: a}}$

now, this is the input for the last or 5th nor gate. this nor gate gives the output as the inversion of its input. hence the final output of the above circuit is, $\mathrm{\overline{\overline{b\cdot \overline{a} \: + \: \overline{b}\cdot \: a}}}$ or, $\mathrm{y \: = \: (a\cdot \overline{b} \: + \: \overline{a}\cdot \: b)}$

this is the output of the xor gate. hence the above nor gate-based circuit is the circuit of xor gate.

thus the output of the above circuit is the same as the output of an xor gate. hence the above circuit represents the circuit diagram of exclusive or gate using nand gates.

the nor gate is a type of universal logic gate, hence we can use only nor gates to realize the xnor logic function.

designing an xnor gate using nor gate

to design an xnor gate using nor gate, we first derive the xnor logic function in terms of nor logic as follows.

the output of xnor gate is given by,

$$\mathrm{y \: = \: ab \: + \: \bar{a} \: \bar{b}}$$

to implement an xnor gate logic using nor gate, we require a minimum of 4 nor gates. the circuit diagram of xnor gate from nor gate is depicted in the following figure:

implementation of xnor gate using nor gate

in this circuit, the output is

$$\mathrm{y \: = \: \overline{\overline{a \: + \: \overline{(a \: + \: b)}} \: + \: \overline{b \: + \: \overline{(a \: + \: b)}}}}$$

$$\mathrm{y \: = \: \overline{\overline{a \: + \: \overline{(a \: + \: b)}}} \: \cdot \: \overline{ \overline{b \: + \: \overline{(a \: + \: b)}}}}$$

$$\mathrm{y \: = \: (a \: + \: \overline{(a \: + \: b)}) \: \cdot \: (b \: + \: \overline{(a \: + \: b)})}$$

$$\mathrm{y \: = \: (a \: + \: (\bar{a} \: \cdot \: \bar{b})) \: (b \: + \: (\bar{a} \: \cdot \: \bar{b}))}$$

$$\mathrm{y \: = \: (a \: + \: \bar{a}) \: (a \: + \: \bar{b}) \: (\bar{a} \: + \: b) \: (b \: + \: \bar{b})}$$

$$\mathrm{y \: = \: (a \: + \: \bar{b}) \: (\bar{a} \: + \: b)}$$

$$\mathrm{y \: = \: a\cdot\bar{a} \: + \: \bar{a}\cdot\bar{b} \: + \: a\cdot b \: + \: b\cdot\bar{b}}$$

$$\mathrm{\therefore \: y \: = \: a\cdot b \: + \: \bar{a}\cdot\bar{b}}$$

this is the desired output of the xnor gate. thus, the above shown nor logic circuit performs the xnor operation.

in digital electronics, nand and nor gates are two universal logic gates that are used to perform boolean operations on multiple input variables. these gates produce an output based on the combination of inputs applied.

nand and nor gates are used as the fundamental building blocks in the digital circuits and systems. we can design and implement the nand and nor gates in different technologies such as dtl, rtl, ttl, and cmos. this chapter deals with implementation of nand and nor gates using cmos technology.

in cmos (complementary metal oxide semiconductor) technology, the nand and nor logic gates are designed by connecting nmos and pmos transistors in series and parallel connections. the block diagram of a 2-input logic gate in cmos technology is shown in the following figure.

before getting deeper into the nand and nor gate using cmos technology. lets first study the basics of nand and nor gates individually.

nand gate

the nand gate is a combination of not gate and and gate, where a not gate connected to the output of the and gate. thus, it is also known as noted and gate.

$$\mathrm{and \: gate \: + \: not \: gate \: = \: nand \: gate}$$

the logic circuit symbol of a two input nand gate is shown in the following figure −

implementation of nand/nor gate using cmos 1

the nand gate produces a low or logic 0 output when all inputs applied to it are high or logic 1. for all other input combinations, it produces a high or logic 1 output.

truth table of nand gate

the truth table of a two input nand gate is shown here −

inputs		output
a	b	y
0	0	1
0	1	1
1	0	1
1	1	0

from this truth table, we can write the boolean expression of the nand gate, as follows.

$$\mathrm{y \: = \: \overline{a\cdot b}}$$

here, y is the output variable, and a and b are the input variables.

nor gate

the nor gate is a universal logic gate in digital electronics. it is a combination of two basic logic gates namely, not gate and or gate, where it is realized by connecting a not gate to the output of the or gate. therefore,

$$\mathrm{or \: gate \: + \: not \: gate \: = \: nor \: gate}$$

implementation of nand/nor gate using cmos 2

the output of the nor gate is high or logic 1, when all its inputs are low or logic 0. for all other input combinations, the output of the nor gate is low or logic 0.

truth table of nor gate

the following is the truth table of a two input nor gate that describing its operation −

inputs		output
a	b	y
0	0	1
0	1	0
1	0	0
1	1	0

from this truth table, we can write the boolean expression of the nor gate, as follows.

$$\mathrm{y \: = \: \overline{a \: + \: b}}$$

here, y is the output variable, and a and b are the input variables.

this is all about the basics of nand and nor gate. let us now discuss the implementation of nand and nor gates using cmos technology.

nand gate using cmos technology

the nand gate can be implemented in cmos technology by using pmos and nmos transistors. the circuit diagram of a two input nand gate in cmos technology is shown in the following figure −

implementation of nand/nor gate using cmos 3

it consists of two pmos transistors q1 and q2 and two nmos transistors q3 and q4. the pmos transistors are connected in parallel between the power supply v_dd and the output terminal y. similarly, the nmos transistors are connected in series between the output terminal y and the ground terminal gnd.

now, let us understand the operation of this cmos nand gate.

case 1: when input a is low and input b is low

in this case, when both inputs a and b are low, the pmos transistors q1 and q2 are on and the nmos transistors q3 and q4 are off. hence, there is a closed path between the supply voltage v_dd and the output terminal y.

thus, the output y will be connected to the voltage level v_dd. also, there is no path between the output terminal and the ground terminal as both nmos transistors are off. under this condition, the output line will maintain the voltage level at v_dd, which indicates the output high.

thus, when a = 0 and b = 0, then y = 1

case 2: when input a is low and input b is high

in this case, the pmos transistor q1 will be on while the pmos transistor q2 will be off. the nmos transistor q3 will be off and the nmos transistor q4 will be on.

for this switching condition of the cmos transistors, the power supply v_dd will get a path to the output terminal through the pmos transistor q1. since, the nmos transistor q3 and q4 are connected in series and the nmos transistor q3 is off. hence, there is no path between the output terminal and the ground terminal.

therefore, the output terminal y maintain the voltage level at v_dd and results in a high output.

thus, when a = 0 and b = 1, then y = 1

case 3: when input a is high and input b is low

in this case, the pmos transistor q1 will be off and the pmos transistor q2 will be on. the nmos transistor q3 will be on and the nmos transistor q4 will be off.

under this switching condition of the cmos transistors, the output terminal will connect to the power supply through the pmos transistor q2. since, both nmos transistors are connected in series and the nmos transistor q4 is off. hence, there is no path between the output terminal and the ground terminal.

therefore, the output line will maintain the voltage level at v_dd and results in a high output.

thus, when a = 1 and b = 0, then y = 1

case 4: when input a is high and input b is high

in this case, both pmos transistors q1 and q2 will be off and both nmos transistors will be on. in this case, there is no path between the output terminal and the power supply v_dd, but there is a direct path between the output terminal and the ground terminal. this results in a ground voltage level at the output terminal and produces a low output.

hence, when a = 1 and b = 1, then y = 0

the operation of this cmos nand gate is shown in the following truth table −

inputs		output
a	b	y
low (0)	low (0)	high (1)
low (0)	high (1)	high (1)
high (1)	low (0)	high (1)
high (1)	high (1)	low (0)

this is all about nand gate implementation using cmos technology and its operation for different input combinations.

let us now discuss the implementation and operation of nor gate using cmos technology.

nor gate using cmos technology

similar to cmos nand gate, we can also design a nor gate using pmos and nmos transistors. the circuit diagram of a two input nor gate using cmos technology is shown in the following figure −

implementation of nand/nor gate using cmos 4

this cmos nor gate is designed by using two pmos transistors q1 and q2 and two nmos transistor q3 and q4. where the pmos transistors are connected in series between the supply voltage v_dd and the output terminal y. the nmos transistors are connected in parallel between the output terminal y and the ground terminal gnd.

now, let us understand how does this cmos circuit operate as a two input nor gate.

case 1: when input a is low and input b is low

in this case, both pmos transistors q1 and q2 will be on and both nmos transistors q3 and q4 will be off.

under this switching condition of the cmos transistors, there is a path between the supply voltage v_dd and the output terminal y through the on pmos transistors. but there is no path between the output terminal y and the ground terminal gnd. this maintains the output at the voltage level v_dd and hence the output will be high.

thus, when a = 0 and b = 0, then y = 1

case 2: when input a is low and input b is high

in this case, the pmos transistor q1 is on, the pmos transistor q2 is off, the nmos transistor q3 is off, and the nmos transistor q4 is on.

since, the pmos transistors q1 and q2 are connected in series and the transistor q2 is off. thus, there is no path between the power supply v_dd and the output terminal y. but there is a connection between the output line y and the ground terminal gnd through the on nmos transistor q4. this sets the output terminal to ground voltage and makes the output low.

therefore, when a = 0 and b = 1, then y = 0

case 3: when input a is high and input b is low

in this condition, the pmos transistor q1 is off, the pmos transistor q2 is on, the nmos transistor q3 is on, and the nmos transistor q4 is off.

in this case, there is no closed path between the power supply v_dd and the output line y due to off pmos transistor q1. but there is a closed between the output line y and the ground terminal gnd through the on nmos transistor q3. hence, the output terminal is connected to the ground potential and makes the output low.

thus, when a = 1 and b = 0, then y = 0

case 4 when input a is high and input b is high

in this case, both pmos transistors q1 and q2 are off and both nmos transistors q3 and q4 are on. under this condition, there is no path between the supply voltage v_dd and the output terminal y. but there is a closed path between the output terminal y and the ground terminal gnd. this maintains the output line at ground voltage level and hence the output will be low.

thus, when a = 1 and b = 1, then y = 0

this complete operation of the cmos nor gate can be summarized in the form of a truth table which is given below.

inputs		output
a	b	y
low (0)	low (0)	high (1)
low (0)	high (1)	low (0)
high (1)	low (0)	low (0)
high (1)	high (1)	low (0)

advantages of nand and nor gates using cmos technology

nand and nor gates implemented in cmos technology offer several benefits over other technologies. some of the key advantages of cmos nand and nor gates are listed here −

cmos nand and nor gates consume relatively low power. this advantage makes these logic gates well-suited to use in battery powered devices.
nand and nor gates designed using cmos technology have high immunity against noise and interference. they can be designed to have a wider range of operating voltage.
the cmos technology offers high-density integration that allows for implementing a large number of nand and nor gates on a single chip. these gates provide symmetrical output characteristics that allow them to integrate with different types of digital circuits seamlessly.
cmos technology is one of the well-established, mature, and cost-effective semiconductor manufacturing technology. hence, the cmos nand and nor gates are relatively easy to manufacture and cost effective.

applications of cmos nand and nor gates

the cmos nand and nor gates are widely used in the following applications due to their benefits and versatility −

cmos nand and nor gates are widely used in the logic circuit designs to perform logical operations.
in digital systems, the cmos nand and nor gates are used to implement arithmetic circuits like adders, subtractors, multipliers, etc.
they are also used in memory units to implement memory cell structures.
cmos nand and nor gates are also used to design multiplexers and demultiplexers.
some other common applications of cmos nand and nor gates include digital signal processing, digital timing circuits, analog to digital conversion, digital communication, etc.

conclusion

the cmos nand and nor gates are widely used in a variety of applications in the field of digital electronics. this type of nand and nor gates offer several advantages such as high efficiency, low power consumption, versatility, low cost, high reliability, etc.

in this chapter, we explained the implementation of nand and nor gates using cmos technology along with their advantages and applications.

memory is one of the important parts in a computer or any other digital system. it is used to hold data and programs required for processing and performing tasks.

memory also affects the performance, efficiency, and speed of the digital system. these days, semiconductor memories are popular, as they provide a very high-speed operation, large storage capacity, and compact size.

here, we will explain the basic to advanced concepts related to semiconductor memory devices.

what is memory?

in the field of digital electronics, the memory is a device that is used to store data and instruction in the digital systems like computers and other microprocessor-based systems. in modern digital systems, the memory is made up of semiconductor materials and known as semiconductor memory.

the memory is the device that provides the storage space in computer or any other digital system where data is to be processed and instructions required for processing are stored.

the memory is divided into a large number of small parts. each part is called a memory cell. each memory cell or location has a unique address assigned to it which varies from zero to total memory size minus one.

for example, if a computer has 64 kb memory size, then this memory unit has 64 1024 = 65536 memory location or cells. hence, the address of these locations ranges from 0 to 65535.

classification of memory

memory is primarily classified into two types, they are: internal memory and external memory.

internal memory

internal memory is also known as primary memory, as it is directed connected to the hardware architecture of the digital system. it is typically installed in the systems motherboard in form of ics.

examples of internal memory include cache memory, ram (random access memory), rom (read only memory), etc.

external memory

external memory is also known as secondary memory. this memory is not directly connected to the hardware architecture of the systems, instead it is connected through cables as a peripheral device.

the external memory is primarily used to provide additional storage space to store data and instructions permanently. examples of external memory are cd, dvd, hdd, ssd, usb drives, etc.

memory hierarchy

memory hierarchy is defined as an arrangement of different types of memory devices used in a digital system depending on their characteristics, primarily speed and capacity. the memory hierarchy helps us to select an appropriate memory to use in our system at a specific level.

a typical memory hierarchy of memory for different memory devices is shown in the following figure −

some of key characteristics of this memory hierarchy, when we go from top to bottom −

capacity in terms of storage increases.
cost per bit of storage decreases.
frequency of access of the memory by the cpu decreases.
access time by the cpu increases.

functional block diagram of memory

a memory is basically a group of multiple storage cells having a support circuit to perform data read/write operations. the following figure depicts the functional block diagram of a typical memory device −

it consists of the following main parts −

address lines

these lines are used to load the address of a specific memory location or cell.

data lines

these lines are used to read and write the data from/to the memory cell.

read and write signal (r/w)

this signal is used to read and write the data from and to the memory cells. when the r signal is high, the data of the selected cell gets loaded on the data line. when the w line goes low, the data on the data line is loaded into the selected memory cell.

chip select signal (cs)

this signal is used to enable or disable the memory chip. it is an active low signal, which means when this signal goes low, the memory chip is enabled and allow the read and write operations to execute. otherwise, the memory chip will be disabled.

important terms related to memory operation

the following are some important terms and definitions which are related to the read and write operations of memory −

write cycle time − the write cycle time is defined as the minimum amount of time for which a valid cell address is available for data writing operation in the cell. typically, it is of the order of 200 ns.
write pulse time − the minimum duration of a write pulse is termed as write pulse time and it is of the order of 120 ns.
write release time − the minimum time for which the memory address is valid before the write pulse is known as write release time.
data setup time − the minimum amount of time for which the data remains valid before the write pulse ends is known as data setup time. typically, it is around 120 ns.
data hold time − the minimum amount of time for which the data remains valid after the write pulse ends is known as data hold time.
read cycle time − the minimum amount of time for which a valid memory address remains available for reading the data from a memory cell is known as read cycle time. it is typically of the order of 200 ns.
access time − the amount of time required to access data from a memory cell is referred to as access time of the memory. it is also of the order of 200 ns.
read to output active time − the minimum time that required for enabling the output buffer after starting of the read pulse is called the read to output active time. typically, this time is of the order of 20 ns.
read to output valid time − the maximum delay time between the beginning of the read pulse and the availability of the valid data at the data output line is known as "read to output valid time".

these are some key terms whose knowledge is required to understand the read and write operations of a memory device.

characteristics of memory devices

in this section, we will focus on studying some key characteristics of memory devices and their definitions and importance −

storage capacity

this parameter denotes the total memory of the device. it is generally expressed in terms of number of bytes that it can store. for example, a memory of 1k 8 bits can store 1024 8 = 8192 bytes of digital data.

unit of data transfer

the number of bits that can be read or written in a single read or write cycle is called the unit of data transfer. in general, the unit of data transfer is equal to the word length or size of the data bus of the processor.

modes of access

it refers to the way in which the data can be read or write to the memory. there are following three modes used in digital memory devices −

sequential access

in this mode, the data is read from or write to the memory in a predefined sequential manner. in other words, to access the second file, we first access the first file, to access the third file, firstly access the first and second files, and so on.

random access

in this mode, we can directly access any memory location in any order.

direct access

this mode is a combination of sequential and random access modes. it is also termed as semi-random access mode.

data transfer rate

it is defined as the amount of data that is read or write in one second. it is generally measured in bits per second. data transfer rate is referred to as bandwidth of memory.

types of memory devices

some of the important classifications of memory devices used in computers and digital systems are listed and explained here.

classification of memory on the basis of nature of data storage −

volatile memory
non-volatile memory

classification of memory on the basis of access modes −

sequential access memory
random access memory

now, let us discus all these types of memories in detail along with their subtypes and characteristics.

volatile memory

a type of memory that requires continuous power supply to maintain the stored data is called a volatile memory. if the power supply to the memory is turned off, the data stored in it will be lost. therefore, it is also termed as temporary memory.

properties of volatile memory

the volatile memory loses its stored data when power supply to it is turned off. volatile memory has fast operational speed; thus, it can read and write data in a short span of time.

volatile memory is used to store data required to be accessed and perform operations. ram (random access memory) is an example of volatile memory.

non-volatile memory

a type of memory which can retain stored data even when no power supply is present is known as non-volatile memory. it is also known as permanent memory and is used for long-term storage of digital data.

properties of non-volatile memory

non-volatile memory stores data permanently. it can retain the stored data even when the power supply is switched off.

non-volatile memory is slower than volatile memory. hence, this memory has longer read and write cycles.

examples of non-volatile memory includes rom (read only memory), magnetic tapes, optical discs, magnetic discs, usb drives, etc.

sequential access memory

a type of memory in which the stored data and information is accessed in a predefined sequential manner is known as a sequential access memory.

sometimes, it is also known as serial access memory, as the stored data is retrieved in a serial order.

in a sequential access memory, the system must search the storage device from the beginning of the memory address until it finds the required piece of data. in other words, to retrieve the desired data, the system must access all memory addresses until it reaches the desired data.

properties of sequential access memory

in a sequential access memory, data retrieval process executes in a sequential manner. where, the system starts from beginning of the memory and go sequential through all memory addresses until the desired data is obtained.

sequential access memory has slower access speed and longer read/write time. magnetic tapes are the examples of sequential access memory.

random access memory

random access memory, also called as direct access memory, is a type of memory in which the desired data can be accessed directly, without going through the preceding data. hence, this memory allows to access any data in any order.

in other words, the direct access memory or random access memory has the ability to read from or write to data in any memory location in the same time. hence, the access time for all the memory cells is the same and it does not depend on the physical location of the cell within the memory array.

properties of random access memory

random access memory allows data to be accessed in any random order. it provides high speed data access i.e., fast read and write operations.

all memory locations of the random access memory are directly accessible to the processing element of the digital system.

examples of random access memory include ram, rom, hard disk, optical disks, and other semiconductor memories, etc.

conclusion

in conclusion, a memory device is an important component in a digital system like computer used to store data and information.

different types of memory devices are used for different purposes. for example, a volatile memory like ram is used to hold temporary data which are required till the process is complete.

on the other hand, a non-volatile memory is used to hold data permanently for a longer period of time. for example, a hard disc is used to store users data in the computer system.

in the last chapter, we had a discussion on memory devices and their characteristics. read this chapter to understand the characteristics of the two most important types of memories named, ram (random access memory) and rom (read only memory) which are used in digital systems like computer, laptops, smartphones, etc.

what is ram?

a ram constitutes the internal memory of the cpu for storing data, program and program result. it is read/write memory. it is called random access memory (ram).

since the access time in ram is independent of the address to the word that is, each storage location inside the memory is as easy to reach as other location & takes the same amount of time. we can reach into the memory at random & extremely fast but can also be quite expensive.

ram is a volatile memory i.e., data stored in it is lost when we switch off the computer or if there is a power failure. hence, a backup uninterruptible power system (ups) is often used with computers. ram is small, both in terms of its physical size and in the amount of data it can hold.

types of ram

ram or random access memory is classified into the following two types −

static ram (sram)
dynamic ram (dram)

lets discuss about these two types of rams in detail.

static ram (sram)

the word "static" indicates that the memory retains its contents as long as power remains applied. however, data is lost when the power gets down due to volatile nature. sram chips use a matrix of 6-transistors and no capacitors. transistors do not require power to prevent leakage, so sram need not have to be refreshed on a regular basis.

because of the extra space in the matrix, sram uses more chips than dram for the same amount of storage space, thus making the manufacturing costs higher. static ram is mainly used as cache memory needs to be very fast and small.

characteristics of sram

the following are some important characteristics of sram −

being a type of ram, the sram is also a volatile memory. thus, it requires a continuous power supply to maintain its stored data. if power supply is removed or switched off, the data stored in the sram will delete.
sram is a high-speed random access memory. sram does not need to be refreshed to maintain its stored data.
sram is made up of semiconductor components called flip-flops which store data. sram has lower storage density. this is mainly because of its complex memory cell structure. this also results in larger physical size.
sram is mostly employed in digital systems in which high-speed data access is important. for example, it is used as cpu cache memory, high-speed buffers, and registers in microprocessors and microcontrollers.
sram is relatively more expensive. this is mainly because of its lower storage density and higher manufacturing cost.

dynamic ram (dram)

dram, unlike sram, must be continually refreshed in order for it to maintain the data. this is done by placing the memory on a refresh circuit that rewrites the data several hundred times per second. dram is used for most system memory because it is cheap and small.

all drams are made up of memory cells. these cells are composed of one capacitor and one transistor.

characteristics of dram

the important characteristics of dram (dynamic random access memory) are listed below −

since dram is also a random access memory, hence it is also a volatile memory and thus requires a continuous power supply to retain its stored data. the data stored in dram is lost, when power supply to is turned off.
in dram, the memory cells are made up of capacitors and transistors. where each memory cell can store a 1-bit of data in the form electric charge in a capacitor.
in dram, to prevent losing stored data due to leakage in capacitor, a refresh circuit is required for periodic refresh cycles. this is the primary reason the term "dynamic" is used in dram.
for dram, the access time is typically of the order in nanoseconds (ns). dram is less expensive than sram.

this is all about ram (random access memory) and its types. let us now discuss about another type of memory device called rom.

what is rom?

rom stands for read only memory. the memory from which we can only read but cannot write on it. this type of memory is non-volatile. the information is stored permanently in such memories during manufacture.

a rom, stores such instruction as are required to start computer when electricity is first turned on, this operation is referred to as bootstrap. rom chip are not only used in the computer but also in other electronic items like washing machine and microwave oven.

types of rom

the following are some important types of read only memory (rom) −

mrom
prom
eprom
eeprom

lets discuss these different types of roms in detail along with their important characteristics.

mrom (masked rom)

the very first roms were hard-wired devices that contained a pre-programmed set of data or instructions. these kinds of roms are known as masked roms. it is inexpensive rom.

since it is a type of rom, thus it is also a non-volatile memory. the mroms are programmed at the time of manufacturing and its data cannot be modified or changed at a later point of time.

characteristics of mrom

the following are some important characteristics of mrom −

mrom is a non-volatile memory. hence, it can retain its data even when power supply is turned off or removed.
mrom is mainly used for storing permanent software and instructions like firmware, bootloader code, and other system data essential for system operations.
in mrom, data and programs are written during the manufacturing process. once it is programmed, the stored data cannot be modified or changed. thus, it is a one-time programmable memory.
another important characteristic of mrom, it is a read-only memory. thus, it supports read only operations.
mrom is an inexpensive type of read only memory.
the major disadvantage of the mrom is its limited flexibility that means once it is programmed, the stored data cannot be changed or deleted.

prom (programmable read only memory)

prom is a read-only memory that can be modified only once by a user. the user buys a blank prom and enters the desired contents using a prom programmer.

inside the prom chip, there are small fuses which are burnt open during programming. it can be programmed only once and is not erasable.

characteristics of prom

here are the important characteristics of the programmable read only memory −

prom also retains its stored data, when the power supply is turned off.
prom is a programmable memory, but it can be programmed by the user only once. then, its stored data cannot be changed, deleted, or rewritten.
in prom, the memory cells are made by using either fuse-based technology, in which storing the data involves blowing of tiny fuses.
prom is also a read only memory, thus it supports read operations only.
like mrom, prom also offers limited flexibility, as the data cannot be changed or erased, once it is programmed.

eprom (erasable and programmable read only memory)

the eprom can be erased by exposing it to ultra-violet light for a duration of up to 40 minutes. usually, an eprom eraser achieves this function.

during programming, an electrical charge is trapped in an insulated gate region. the charge is retained for more than ten years because the charge has no leakage path. for erasing this charge, ultra-violet light is passed through a quartz crystal window (lid). this exposure to ultra-violet light dissipates the charge. during normal use, the quartz lid is sealed with a sticker.

characteristics of eprom

some of the key characteristics of eprom are highlighted below −

eprom provides a permanent storage for data even in the absence of power supply.
eprom is an electrically programmable memory. hence, it can be programmed by applying specific voltage levels to its write circuit.
eprom can be erased multiple times by exposing it to uv rays for around 20 to 30 minutes. then, it can be reprogrammed again.
eprom chips have a quartz window on its top. this is provided to penetrate the uv rays to erase the stored data.
eprom provides the high storage density. hence, it can hold large amounts of data in a relatively small physical space.
eprom is slower to write, that can affect overall performance of the system.

eeprom (electrically erasable and programmable read only memory)

the eeprom is programmed and erased electrically. it can be erased and reprogrammed about ten thousand times. both erasing and programming take about 4 to 10 ms (millisecond).

in eeprom, any location can be selectively erased and programmed. eeproms can be erased one byte at a time, rather than erasing the entire chip. hence, the process of re-programming is flexible but slow.

characteristics of eeprom

the important characteristics of electrically erasable programmable read only memory are highlighted below −

being a rom, eeprom stores data permanently.
eeprom can be erased and reprogrammed electrically and does not require any special equipment or uv rays for erasing the stored data.
eeprom can be erased and reprogrammed multiple times.
eeprom also provides random data access capabilities. this feature allows for efficient and fast data manipulation and management.
eeprom consumes very less power. hence, it is better suited to use in battery-powered devices where energy efficiency is important.
eeprom is a cost effective read only memory device designed use in modern digital systems.

conclusion

in this chapter, we explained the basics ram and rom along with their different types and characteristics.

cache memory is a very high-speed semiconductor memory which can speed up the cpu. it acts as a buffer between the cpu and main memory. it is used to hold those parts of data and program which are most frequently used by cpu. the parts of data and programs are transferred from the disk to the cache memory by the operating system, from where the cpu can access them.

in this chapter, we will explain in detail about cache memory along with its advantages and disadvantages.

what is cache memory?

in digital systems like computers, the cache memory is a high-speed volatile semiconductor memory used to store data and instructions frequently accessed by the central processing unit of the system.

the cache memory acts as a buffer between the processing element and main/primary memory, more specifically ram (random access memory). it is mainly used to provide a faster access to the recent and most frequently used data and programs.

the cache memory is employed for improving the performance and efficiency of the digital systems, as it reduces the time required for accessing the data.

cache memory design

in this section of the article, we will discuss different concepts involved in the design of cache memory

purpose of the cache memory

the main purpose of the cache memory is to store frequently used data and instructions. this helps in reducing the access time.

size of the cache memory

it is found that small size cache memory results in better performance improvement of the system.

cache memory hierarchy

cache memory is generally organized in multiple hierarchy levels, where each level is called a cache level or cache layer. a computer system typically has multiple cache levels, most common of them are l1 (level 1 cache), l2 (level 2 cache), and l3 (level 3 cache). here, the cache memory l1 is the smallest, fastest and closest to the cpu of the system, while the l2 and l3 cache memories are larger and slower than l1 cache.

structure of cache memory

cache memory is typically divided into blocks of a fixed size. each block has a specific data storage capacity. the structure of the cache memory is formed by grouping all these blocks together into cache sets.

mapping techniques for cache memory

the mapping techniques are used to determine how the memory blocks are mapped to cache blocks. the following three types of cache mapping techniques are commonly used

direct mapping − direct mapping is a simple cache mapping technique in which each memory block is mapped into a certain cache block. although, this technique can lead to a high rate of conflicts.
fully associative mapping − in this mapping technique, each memory block can be placed in any cache block, hence this technique has high flexibility. however, it requires addition hardware.
set associative mapping − this mapping technique is a combination of direct and fully associative mappings. in this technique, the cache memory is divided into cache sets, and each memory block can be placed in any cache block within its corresponding cache set.

cache replacement algorithms

when a memory block is required to be accessed into a cache block that is already occupied, then a cache replacement algorithm is needed to determine which memory block should be replaced to free up space in the cache memory for the new memory block.

the following three are the common cache replacement algorithms

first-in first-out (fifo) algorithm − this algorithm replaces the memory block that exists in the cache memory the longest.
least recently used (lru) algorithm − this algorithm replaces the memory block that has been fetched least recently.
random replacement (rr) algorithm − this algorithm replaces any memory block randomly.

performance of cache memory

the performance of the cache memory is generally measured in terms of its hit rate. the hit rate specifies the percentage of memory accesses that result in cache memory hits. a high hit rate indicates that a significant portion of the memory accesses is satisfied from the cache memory. this provides enhanced system performance.

all these are the fundamental concepts of cache memory design. now, lets have look into the advantages and disadvantages of cache memory design.

types of cache memory

cache memory is classified on the basis of "levels". where, each level describes its accessibility and closeness to the processing element of the digital system.

the classification of cache memory is done in the following three levels −

l1 (level 1) cache memory

it is also known as primary cache memory. the l1 cache memory is the fastest one. but it is very small in size and mainly used in the processor chip in the form of cpu cache.

l2 (level 2) cache memory

it is also called secondary cache memory. it has more capacity as compared to the l1 cache memory. it can be used in the processor chip as cpu cache or it can be a separate chip.

l3 (level 3) cache memory

this one is a specialized cache memory designed to enhance the performance of l1 and l2 cache memories. however, the l3 cache memory is significantly slower than l1 or l2 cache memories.

features of cache memory

the key features of cache memory are listed below −

cache memory is faster than main memory.
it consumes less access time as compared to main memory.
it stores the program that can be executed within a short period of time.
it stores data for temporary use.

advantages of cache memory

in digital systems, the cache memory provides several advantages, as it improves the overall performance and efficiency of the system. some of the key benefits of the cache memory are highlighted below −

cache memory provides a faster data access speed and reduces the total access time. this characteristic of the cache memory helps to speed up the execution of tasks.
cache memory helps to reduce the memory latency by storing recent and most frequently used data and instructions. also, it minimizes the dependency on slower primary memory or ram. this feature also results in improved system performance and efficiency.
cache memory operates at the same speed as the cpu. hence, it can provide a steady stream of input data and instructions that reduces the idle time of the cpu. therefore, it also improves the cpu utilization.
cache memory bridges the gap between the high-speed, expensive cache memory and the slow-speed, cheap main memory. it provides a balance between speed, capacity, and cost.

disadvantages of cache memory

however, the cache memory offers several advantages. but it also has some disadvantages which are listed below −

cache memory has a very smaller storage capacity. thus, it cannot be used to hold all the data and instructions required by the processing unit.
cache memory is expensive to the design and manufacture. it also increases the overall complexity of architecture of the digital system.
sometimes, the cache pollution may occur when irrelevant data stored in the cache memory and there is no enough space for useful data. this significantly degrades system performance.

conclusion

in conclusion, the cache memory is a high-speed semiconductor memory primarily used in digital systems to improve their performance and efficiency. the use of cache memory reduces the data access time and speeds up the task execution. however, being a quite expensive memory, it can increase the overall cost of the system.

in this chapter, we covered all the important concepts related to cache memory such as its purpose, features, advantages, and disadvantages.

programmable logic devices (plds) are a collection of integrated circuits which are configured to perform various logical functions. plds play an important role in the field of engineering and technology, as they form the basis of innovation and support engineers to develop automated digital systems to improve process flexibility and efficiency. here, "programmable" means defining a function that can be performed multiple times without human intervention.

programmable logic devices (plds) are the integrated circuits. they contain an array of and gates & another array of or gates. there are three kinds of plds based on the type of array(s), which has programmable feature.

programmable read only memory
programmable array logic
programmable logic array

the process of entering the information into these devices is known as programming. basically, users can program these devices or ics electrically in order to implement the boolean functions based on the requirement. here, the term programming refers to hardware programming but not software programming.

in this chapter, we will explain the basic concepts of programmable logic devices, their types, advantages, limitations, and applications.

programmable read only memory (prom)

read only memory (rom) is a memory device, which stores the binary information permanently. that means, we cant change that stored information by any means later. if the rom has programmable feature, then it is called as programmable rom (prom). the user has the flexibility to program the binary information electrically once by using prom programmer.

prom is a programmable logic device that has fixed and array & programmable or array. the block diagram of prom is shown in the following figure.

here, the inputs of and gates are not of programmable type. so, we have to generate 2ⁿ product terms by using 2ⁿ and gates having n inputs each. we can implement these product terms by using nx2ⁿ decoder. so, this decoder generates n min terms.

here, the inputs of or gates are programmable. that means, we can program any number of required product terms, since all the outputs of and gates are applied as inputs to each or gate. therefore, the outputs of prom will be in the form of sum of min terms.

example

let us implement the following boolean functions using prom.

$$\mathrm{a(x,y,z)\:=\:\sum m\left ( 5,6,7 \right )}$$

$$\mathrm{b(x,y,z)\:=\:\sum m\left ( 3,5,6,7 \right )}$$

the given two functions are in sum of min terms form and each function is having three variables x, y & z. so, we require a 3 to 8 decoder and two programmable or gates for producing these two functions. the corresponding prom is shown in the following figure.

here, 3 to 8 decoder generates eight min terms. the two programmable or gates have the access of all these min terms. but, only the required min terms are programmed in order to produce the respective boolean functions by each or gate. the symbol x is used for programmable connections.

what is a programmable logic device?

a programmable logic device (pld) can be defined as an integrated circuit (ic) which can be programmed to perform specific functions. here, programming means we can define a set of instructions that can be executed to perform the functions multiple times without need of any human intervention.

the primary need of developing plds is occurred to implement digital logic functions that can copy the behavior of conventional logic circuits and replicate it many times. however, the plds are different from normal digital logic circuits in terms of programmability, which means we can define the desired logic functions by setting a collection of instructions in the device.

types of plds

based on the type of device used, programmable logic devices (plds) can be classified into the following two types −

bipolar plds
cmos plds

let us discuss each type of programmable logic device in detail.

bipolar plds

bipolar plds are the types of programmable logic devices in which bipolar junction transistor (bjt) is the main functional device. bipolar plds are the older versions of programmable logic devices. thus, they were commonly used before the development of cmos plds.

the following are some important characteristics of the bipolar programmable logic devices −

bipolar plds provide fast switching speeds and hence they can operate at higher frequencies.
bipolar plds are better suited for applications involving rapid signal processing and require fast response times.
bipolar plds require more power to operate.
bipolar plds have better immunity to electronic noise and interference.

all these characteristics make the bipolar programmable logic devices well-suited to use in the applications where high-speed operation and reliability are critical, such as aerospace, military, and telecommunications systems.

cmos plds

cmos plds stand for complementary metal oxide semiconductor programmable logic devices. as their name implies, cmos plds use the cmos transistors i.e., nmos (n-channel metal oxide semiconductor) and pmos (p-channel metal oxide semiconductor) transistors as the fundamental component.

cmos plds are basically the modern versions of plds and are widely used in modern digital systems due to their numerous advantages.

some important characteristics of cmos plds are described below −

cmos plds require very less amount of power to operate. hence, this characteristic makes the cmos plds well-suited to use in battery-power devices where energy efficiency is an important factor.
cmos plds are more reliable and robust. as they are designed to withstand against various environmental factors like high/low temperatures, voltage fluctuations, and different radiation interferences.
cmos plds are also excellent in terms of scalability.

cmos plds are newer pld devices and hence are very commonly used in various modern electronics devices like consumer electronics, medical equipment, industrial automation systems, automotive systems.

pld programming languages

in the case of programmable logic devices (plds), several different types of hardware description languages (hdls) are used to program them. using these pld programming languages, engineers and designers can define the behavior and logical functionality of the pld circuit.

some of the most commonly used pld programming languages are described here −

vhdl

vhdl stands for vhsic hardware description language. it is a standardized hardware description language used for modelling and simulating digital circuits and systems. using vhdl, engineers and developers can specify the structure and functionality of the digital circuits. vhdl is a best suited programming language for both combinational and sequential circuits because of its concurrent and sequential descriptions support.

vhdl is one of the most widely used programming language for designing and verification of highly complex digital circuits and systems like plds, asics, fpgas, and more.

verilog

verilog is also a hardware description language (hdl) used for designing and programming of plds. similar to vhdl, verilog also supports the concurrent and sequential descriptions that empower engineers and designers to define the structure and behavior of digital circuits.

this programming language is most commonly used in semiconductor industries for designing and programming different kinds of digital systems.

palasm

palasm stands for programmable array logic assembler. it is another hardware description language (hdl) and assembler used for programming programmable logic devices (plds). in the case of palasm, the behavior, logic function, and structure of plds are described using a textual language format. thus, the developers have to write palasm code to describe the desired logic functions and interconnections. after that these codes are assembled into a format which is suitable for programmable logic devices.

however, palasm is an older hardware description language that was very commonly used in the 1980s and early 1990s for developing pld-based logic circuits.

abel

abel stands for advanced boolean expression language. it is a high-level hardware description language developed for programming the programmable logic devices (plds).

in abel, the logic equations, truth tables, and register transfer level design descriptions are specified using a clearly readable syntax. then, the abel compiler translates all these design descriptions into a format suitable for programming the desired plds. abel was a very commonly used user-friendly hardware description language in the 1990s.

cupl

cupl stands for compiler for universal programmable logic. it is another hardware description language (hdl) and compiler used for programming different kinds of plds. in this programming language, the logic functions, truth tables, and sequential logic instructions are specified in the form of simple syntax.

this hdl language was also very popular in the 1990s and early 2000s and was used for designing pld based logic circuits.

all these are some important programming languages used to design and program the programmable logic devices. the languages palasm, abel, and cupl are mainly in low-complexity devices. whereas, vhdl and verilog are used to program the modern highly-complex plds.

advantages of programmable logic devices

programmable logic devices (plds) have numerous advantages that make them vital tools in the field of digital system design. some of the important benefits of programmable logic devices are listed here −

programmable logic devices (plds) are easy to program and reprogram. hence, they provide significant flexibility in terms of designing and implementation of a variety of logic functions.
plds allow for designing custom logic circuits to fulfil the specific requirements of applications. this can be done by programming the internal logic circuits of the device.
plds can be used in prototyping and testing of digital circuits which help in new product development at a faster rate. by speeding up the product development process, plds help to reduce the time and cost involved in hardware design.
plds provide a fast and cost-effective way of developing medium to complex digital logic circuits and systems. plds help to develop simple, less expensive, and compact digital systems by integrating a large number of logic functions and components into a single device.
plds also support modern processing techniques like parallel processing, pipeline processing, etc. this feature helps to achieve high performance by simultaneous execution of logic functions.

limitations of programmable logic devices

programmable logic devices (plds) offer several advantages as discussed above, but they also have certain limitations. the following are some of the key limitations of programmable logic devices −

a programmable logic device can be designed to support a finite number of logic functions and elements. thus, the implementation of complex digital circuits may require multiple devices.
a pld typically has a fixed number of input/output (i/o) pins. this limitation can cause an issue in terms of connectivity and interfacing with external/peripheral devices.
programming a pld requires knowledge of hardware description languages (hdls) and design tools. sometimes plds can malfunction due to unintentional reprogramming or data corruption.
plds do not have inherent support for complex arithmetic operations and other high-level programming operations that are used in general purpose processors. therefore, developers have to implement such operations and functionalities through custom logic designs.

applications of programmable logic devices

programmable logic devices (plds) are used in a wide range of applications across different fields and industries to design digital logic circuits and implement various logic functions. some common applications of programmable logic devices are listed below −

plds are widely used in embedded systems to perform different real-time operations like controlling, interfacing, and processing of data.
in the field of digital signal processing, plds are used to design digital filters, develop modem algorithms, perform signal processing, etc.
plds play an important role in communication systems, as they help in performing various operations like signal routing, data encryption and decryption, protocol conversion, and more.
in the field of aerospace and defence, plds are employed for accomplishing various critical functions like flight control, operating radar systems, guiding missiles, encryption of confidential data and more.
plds are also used in robotics and industrial automation to control and monitor the operations of machinery.
in medical equipment, plds are used for automated high-speed data processing, real-time analysis of medical data, patient monitoring, etc.

conclusion

in conclusion, a programmable logic device is a digital device that can be programmed or trained to perform a specific logic function. it is primarily used for automation and efficiency improvement purposes in various applications.

in this chapter, we explained the basics, types, advantages, limitations, and applications of plds. in the upcoming chapter, we will explore different kinds of programmable logic devices along with their features and characteristics.

in this chapter, we will talk about programmable logic array (pla), its block diagram, and applications. the programmable logic array (pla) is a type of programmable logic device (pld). historically, pla is the first pld device. it contains an array/matrix of and and or gates whose configuration is done as per the needs of applications.

in a pla, a set of fusible links is used to establish or remove the contact of a literal in the and operation or contact of a product term in the or operation. therefore, a pla is a type of pld that allows both and matrix and or matrix to program.

in digital electronics, plas are used to design and implement a variety of complex combinational circuits. however, some plas also have a memory element, hence they can be used to implement sequential circuits as well.

block diagram of pla

a programmable logic array (pla) is a type of fixed architecture programmable logic device (pld) which consists of programmable and and or gates. a pla contains a programmable and array which is followed by a programmable or array.

the block diagram of the pla is shown in the following figure −

it consists of the following main components −

input buffer

the input buffer is used in pla to avoid the loading effect on the source that drives the inputs.

and array/matrix

the and array/matrix is used in pla to generate the product terms.

or array/matrix

in a pla, the or array/matrix is used to generate the desired output. this is done by oring the product terms to produce the sum terms.

invert/non-invert matrix

it is a buffer used in plas to set the output to active-high or active-low.

output buffer

this buffer is used at the output side. it is mainly provided to increase the driving capability of the programmable logic array (pla).

combinational logic design using pla

in the field of digital electronics, the plas are extensively used for designing combinational logic circuits. the greatest advantage of designing combinational circuits using plas is that pla consist of programmable and and or arrays which allows to implement custom desired logic functions.

the step-by-step procedure to design a combinational logic circuit using plas is explained below −

step 1 − develop a pla program table that shows the inputs, product terms, and outputs.

step 2 − design the and matrix that can generate the desired product terms.

step 3 − design the or matrix that can generate the desired output.

step 4 − design the invert/non-invert matrix to set the active-low or active-high output.

step 5 − finally, program the pla by utilizing the pla program table.

let us understand this process of combinational circuit design using pla with the help of an example.

example

design a full-adder circuit using programmable logic array (pla).

solution

a full-adder consists of three-inputs and two outputs. since it has 3 inputs, thus there are total 8 product terms which are given in the following truth table of the full adder −

inputs			outputs
a	b	c_in	s	c_out
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

from this truth table, the output sum (s) and the output carry (c_out) are given by,

$$\mathrm{s \: = \: \sum \: m(1,2,4,7)}$$

$$\mathrm{c_{out} \: = \: \sum \: m(3,5,6,7)}$$

thus, their boolean expressions will be,

$$\mathrm{s \: = \: \overline{a} \: b \: \overline{c_{in}} \: + \: \overline{a} \: \overline{b} \: c_{in} \: + \: a \: \overline{b} \: \overline{c_{in}} \: + \: a \: b \: c_{in}}$$

$$\mathrm{c_{out} \: = \: a \: b \: + \: b \: c_{in} \: + \: a \: c_{in}}$$

from these two boolean expressions, we can see that there are seven product terms and two sum terms. the pla program table for this full-adder circuit is shown below −

sr.no	product terms	inputs			outputs
sr.no	product terms	a	b	c_in	s	c_out
1	$\mathrm{\overline{a} \: b \: \overline{c_{in}}}$	0	1	0	1	-
2	$\mathrm{\overline{a} \: \overline{b} \: c_{in}}$	0	0	1	1	-
3	$\mathrm{a \: \overline{b} \: \overline{c_{in}}}$	1	0	0	1	-
4	$\mathrm{a \: b \: c_{in}}$	1	1	1	1	-
5	$\mathrm{a \: b }$	1	1	-	-	1
6	$\mathrm{b \: c_{in}}$	-	1	1	-	1
7	$\mathrm{a \: c_{in}}$	1	-	1	-	1
					t	t

in this pla program table, "1" stands for the connection and "-" stands for the absence of the product term in the output. "t" stands for true and it represents the active-high output.

the pla circuit diagram of the full-adder is shown in the following figure.

this example illustrates the complete step-by-step procedure to implement a combinational logic circuit using pla.

advantages of plas

the following are some key advantages of programmable logic arrays (plas) that make them indispensable in the field of digital electronics −

plas provide flexibility in terms of design and implementation of a variety of digital logic operations. plas can be used to implement custom logic functions required to fulfil the needs of different applications.
plas also minimize the time required to design and develop a new digital circuit or system.
plas provide a less expensive way of implementing highly complex digital logic functions. plas eliminate the need of discrete components to implement a logic function, hence they result in space efficiency.
since plas are programmable, they can be modified on their designs without re-fabricating the entire circuit.

disadvantages of plas

however, plas offer several advantages as discussed above. but they also have some disadvantages which are listed below −

for a large number of inputs and outputs, plas are highly complex to design and implement. being a fixed architecture device, plas have limited performance in terms of speed and processing power.
a pla is generally optimized for a specific application, as it has a fixed number of and gates and or gates. this constraint disallows the designers to implement highly complex logic functions with the same pla.
program a pla is a time consuming and complex process.

applications of plas

programmable logic arrays (plas) are widely used in various applications across different fields. the following are some common applications of plas −

plas are used in the field of digital signal processing to implement various logical functions, such as filtering, convolution, fourier transformation, etc.
in control systems, plas are used to implement control logic functions of various components like feedback, pid controllers, state machines, etc.
plas are used to perform different types of arithmetic operations like addition, subtraction, multiplication, and division.
plas also find their application in the field data compression and encryption technologies. plas are used in digital communication systems and networking equipment to implement algorithms for protocol handling, packet processing, error detection and correction, and more.
plas are also used in different measuring instruments such as digital oscilloscopes, protocol analyzers, logic analyzer, etc.

conclusion

a pla is nothing but a kind of digital logic device used to implement complex digital functions without need of discrete components like and gates, or gates, etc. in this chapter, we explained the basics and applications of programmable logic arrays (plas).

in the previous chapter, we explained programmable logic array (pla) which is a first programmable logic device (pld). this chapter will deal with another type of programmable logic device called programmable array logic (pal).

the primary difference between pla and pal is that in a pla device, both and array and or array are programmable, whereas in the case of pal, the or array is fixed while the and array is programmable. a programmable array logic (pal) also consists of arrays of and and or gates.

the most significant advantage that the pal has is that it is very easy to program, as it contains only a programmable and gate array, although it is not as flexible as the pla.

what is a pal?

in the field of digital electronics, there are several different types of programmable logic devices or plds. the programmable array logic (pal) is also a type of pld used to design and implement a variety of custom logic functions. these programmable array logic devices allow digital designers to develop complex logic structures with high flexibility and efficiency.

construction-wise, a pal device consists of an array of programmable and gates connected to a fixed array of or gates. this array structure helps to implement various logic functions by interconnecting the input lines, and gates and or gates.

block diagram of pal

similar to pla, the programmable array logic (pal) is also a type of fixed architecture logic device having an array of programmable and gates and an array of fixed or gates as shown in the following figure −

from this block diagram, it can be seen that a pal consists of the following three main components −

input buffers
and gate array
or gate array

these components are connected together through a programmed connection indicated by "x". in practice, these programmed connections can be made through eprom cells or other programming technologies.

combinational logic design using pal devices

we can design combinational logic circuits using programmable array logic (pal) devices. while designing combinational logic using pal, it is important to note that the boolean expression in the sum products form must be simplified to fit into each section of the pal.

because the array of or gates is fixed, the number of product terms fed to each or gate cannot be changed. if there is a situation when the number of product terms are more, then the boolean function must be implemented for that section.

let us understand the combinational logic design using pal devices with the help of examples.

example

consider a combinational logic circuit which has 3 inputs and 2 outputs. the logic functions for the outputs are given below. implement this circuit using pal.

$$\mathrm{x(a,b,c) \: = \: \sum \: m(1,2,4,6)}$$

$$\mathrm{y(a,b,c) \: = \: \sum \: m(0,1,3,6,7)}$$

solution

obtaining the boolean expressions for the given logic functions,

combinational logic design using pal devices

from these k-maps, we get,

$$\mathrm{x \: = \: a\overline{c} \: + \: b\overline{c} \: + \: \overline{a} \: \overline{b} c}$$

$$\mathrm{y \: = \: \overline{a} \:\overline{b} \: + \: bc \: + \: ab}$$

now, prepare the pal program table for these output functions, which is given below −

product terms		and gate inputs
product terms		a	b	c
1	$\mathrm{a \: \overline{b}}$	1	-	0
2	$\mathrm{b \: \overline{c}}$	-	1	0
3	$\mathrm{\overline{a} \: \overline{b} \: c}$	0	0	1
4	$\mathrm{\overline{a} \: \overline{b}}$	0	0	-
5	$\mathrm{b \: c}$	-	1	1
6	$\mathrm{a \: b}$	1	1	-

now, let's implement the pal logic circuit as per this table. this circuit diagram is shown in the following figure −

this is how we can implement a logic function using programmable array logic (pal).

advantages of pal

in the field of digital electronics, programmable array logic (pal) is widely used in combinational and sequential circuit designing due to the several advantages it offers.

pal devices provide greater flexibility in design and implementation of custom logic functions, as it can be programmed by making interconnections between the input lines and the and gates so that it can meet the requirements of a specific application.
pal devices also provide less expensive ways of implementing complex logic functions. this is because pals eliminate the requirement of custom fabrication processes due to its ability to program.
pals also help to minimize the time required for developing and launching the electronic products.
due to their high integration density, pals allow for implementing multiple logic functions within a single device. consequently, they help in developing compact and efficient designs.

disadvantages of pal

however, programmable array logics (pals) have several advantages as given above, but they also have some disadvantages as listed below −

pal devices have some limitations in terms of complexity in the implementation of logic functions. this is because, a pal contains a certain number of input lines, and gates, and or gates. thus, if we need to implement a complex logic function, then we can require multiple pals.
pal devices have a fixed architecture which contains an array of fixed or gates and an array of programmable and gates. therefore, these devices cannot be used to implement certain logic functions.
since pals have a finite number of input and output lines. this results in a limit in terms of the i/o connectivity of the electronic device.
it is very complex and time-consuming process to program a pal device. it also requires some specialized tools and expertise.

applications of pal

programmable array logics (pals) are extensively used in a variety of applications in the field of digital electronics. some common applications of pals are listed below −

pals are used in embedded systems for implementing control logics, providing interfacing between different components, sensors, and other subsystems, and performing various signal processing tasks like filtering, modulation, demodulation, signal conditioning, etc.
in communication systems, pals are employed for implementing encoding and decoding algorithms, protocol processing, error detection and correction, multiplexing and demultiplexing, etc.
pals are also used in the field of automotive electronics for implementing control logics for managing engine functions, fuel injection, emission control system, anti-lock braking system, audio system, navigation, and driver assistance system.
in industrial automation and robotics, the pals play an important role, as they help to develop logic functions for controlling and monitoring industrial processes, sensors, and other components.
pals are also used in consumer electronics like washing machines, microwave ovens, home automation systems, etc. to implement their control functions.

conclusion

a pal is a type of programmable logic device used to implement combinational and sequential logics and is used as a versatile device across a wide range of fields.

due to its greater flexibility, easy programmability, and reliability, pal has become an important tool in the field of digital electronics.

what is a field-programmable gate array

a field-programmable gate array (fpga) is a type of programmable logic device (pld) that provides high degree of flexibility and can be used for implementing complete digital system on a single chip. it contains an array of identical logic cells that can be programmed. by programming these logic cells or blocks, fpgas can be used to perform various logic functions. also, we can interconnect them to implement complex digital systems.

fpgas also have several input/output (i/o) blocks to create interface between external devices and the fpgas internal logic circuit. they also consist of a memory element to store the programs that specifies the operational behavior of the logic cells and programmable interconnects.

in order to program fpgas, there are various hardware description languages (hdls) available like verilog or vhdl. these programming languages are used to define the desired functionality and behavior of the digital system.

the general block diagram of an fpga is depicted in the following figure.

components of fpga

it consists of the following main components −

configurable logic blocks (clbs)
i/o blocks
programmable interconnects

the configurable logic block consists of multiplexers, flip-flops, and array of combination logic circuits. th i/o blocks provide pins to connect external devices with the fpga. the programmable interconnect is basically a switching matrix structure that provides interconnection between clb and i/o blocks inside the fpga.

certainly! the classification of fpgas into low-end, mid-range, and high-end categories is based on their performance, complexity, gate density, and power consumption. let's delve deeper into each category −

types of fpgas

depending on the applications, fpgas can be classified into the following main types −

low-end fpgas
mid-range fpgas
high-end fpgas

let us now discuss these different types of fpgas in detail.

low-end fpgas

low-end fpgas are primarily designed to consume least power than the mid-range and high-end fpgas. thus, they are well-suited to use in battery-powered devices and other applications where energy efficiency is critical.

in low-end fpgas, a smaller number of logic gates are used, hence they use less resources for implementing complex logic systems. also, these fpgas have a less complex architecture. some common applications of low-end fpgas include simple control systems, basic signal processing systems, and low-cost consumer electronics.

mid-range fpgas

mid-range fpgas take more power than low-end fpgas but less power than high-end fpgas. this is mainly because the mid-range fpgas consist of a larger number of logic gates as compared to low-end fpgas. this in turn increases the overall complexity of the circuit. although, these fpgas offer a balance between performance and efficiency.

since mid-range fpgas provide a larger number of resources, they allow to implement more complex digital circuits.

these fpgas are used in a wide range of applications such as digital signal processing, communication systems, embedded systems, industrial automation systems, telecommunication devices, medical equipment, etc.

high-end fpgas

high-end fpgas consume more power than both low-end and mid-range fpgas. this is because they use a larger number of logic gates and also have higher operating frequencies. although, these fpgas are supposed to be exceptional in terms of performance and processing efficiency.

due to availability of large number resources, the high-end fpgas can be used for implementing highly complex logic circuits and systems. also, they provide the highest level of flexibility and performance.

some common applications where the high-end fpgas are used include high-speed processing systems, real-time data analysis systems, data centers, high-performance computing systems, aerospace and defense systems, etc.

advantages of fpgas

fpgas offer numerous advantages over other types of programmable logic devices. some of the major advantages of fpgas are listed below −

fpgas provide a greater flexibility and re-configurability, as they can be programmed or reprogrammed to implement different logic functions to meet the requirements of specific applications without need of hardware alteration or redesign.
fpgas allow to develop digital systems in less time.
fpgas have high performance and processing capabilities. hence, they can execute complex algorithms and tasks more efficiently.
fpgas can be customized and optimized to meet the requirements of specific applications.
fpgas also support parallelism and pipelining. these technologies allow to enhance the overall system performance and throughput.

disadvantages of fpgas

fpgas offer several advantages as listed above, but they also have certain disadvantages. some of the main disadvantages of fpgas are highlighted here −

fpgas are more expensive than other types of programmable logic devices.
fpgas are complex to design and implement and require more time and expertise in hardware description languages (hdls) and system design tools.
fpgas are more susceptible to security threats than other types of programmable logic devices.

applications of fpgas

fpgas are extensively used in several applications across a wide range of industries. the following are some common applications of fpgas −

fpgas are used in the field of digital signal processing to accomplish tasks such as audio-video signal processing, speech recognition, image processing, etc.
fpgas are used in the implementation of complex algorithms and real-time signal processing functions.
fpgas are used in various communication and networking devices such as routers, switches, network processing units, etc.
in communication systems, fpgas are employed for implementing protocol processing algorithms, packet handling algorithms, encryption-decryption techniques, error detection and correction mechanisms, etc.
fpgas are used in a variety of electronic systems such as embedded systems, industrial automation systems, automotive electronics, consumer electronic devices, etc.
fpgas are used to perform high-end processing tasks such as scientific computation, data analysis, machine learning and artificial intelligence tasks.
fpgas are also integral parts in various medical equipment such as mri (magnetic resonance imaging), ct (computed tomography) scan, ultrasound systems, x-ray machines, etc.

conclusion

in conclusion, fpgas are programmable logic devices used in implementing a complex digital system in the form of a single integrated circuit chip. due to their high performance and computing capabilities, they are used in a diverse range of applications across various industries.

a logic family is defined as a set of electronic circuit designs that have similar characteristics in terms of technical parameters such as logic levels, voltage levels, switching speed, power consumption, noise immunity, etc. the logic families play an important role in the field of digital electronics and allows to implement various logic functions and operations.

depending on the fabrication technology, the logic families can be classified into the following two types −

unipolar logic family
bipolar logic family

a logic family that utilizes unipolar electronic devices like mosfets as their main element is known as a unipolar logic family. some examples of unipolar logic families include pmos, nmos, and cmos.

on the other hand, a bipolar logic family is one that utilizes bipolar electronic devices such as transistors and diodes. the bipolar logic families can be further classified into the following types −

resistor-transistor logic (rtl)
diode transistor logic (dtl)
transistor-transistor logic (ttl)

let us now discuss about each of these logic families in detail.

resistor-transistor logic (rtl)

as the name implies, this logic family utilizes resistors and transistors as their key elements. in the rtl family, the transistors operate in the cut-off or saturation regions depending on the input voltage applied to them. the rtl family was one of the earliest logic families used in the field of digital electronic design.

in short, in the rtl family, the logic circuits are designed using resistors and transistors only.

for example, the circuit of a two-input resistor-transistor logic nor gate is shown in the following figure. here, a and b are the inputs and y is the output of the gate.

the operation of this rtl nor gate for different input combinations is highlighted in the following table −

input a	input b	transistor t₁	transistor t₂	output y
0	0	off	off	1
0	1	off	on	0
1	0	on	off	0
1	1	on	on	0

similarly, we can also implement other types of logic gates as well.

advantages of rtl family

the following are some key advantages of resistor-transistor logic family −

electronic circuits designed using rtl logic family are simple in design, as they consist of a minimum number of resistors and transistors.
circuits manufactured in rtl family are less expensive. these circuits consume less amount of power than circuits implemented in other logic families.

disadvantages of rtl family

the following are some major drawbacks of resistor-transistor logic families −

rtl circuits have low noise margin. this limitation makes them susceptible to noise and interference.
these circuits have poor fan-out.
rtl circuits are slower in operation due to high propagation delay.
rtl family is not suitable for designing complex circuits due to some practical limitations in terms of design scalability and performance.

applications of rtl family

resistor-transistor logic (rtl) family finds some limited applications in the field of digital electronics. some common applications of rtl family are listed below −

rtl family is cost-effective and easy to understand and design. for this reason, it is widely used for educational purposes in labs and classrooms to demonstrate digital electronic concepts to students.
rtl family is also used to design circuits for low-frequency control applications. due to simplicity and ease of implementation, rtl family can be used for prototyping and experimental purposes.

diode transistor logic (dtl)

in diode-transistor logic (dtl) family, the diodes and transistors are the key elements combinedly used to implement digital logic functions.

the following example circuit demonstrates the electronic circuit design in dtl family.

it is a two-input nand gate. where, a and b are inputs of the nand gate and y is the output of the gate.

the operation of this two-input nand gate is explained in the following truth table −

input a	input b	diode d₁	diode d₂	transistor t	output y
0	0	forward biased	forward biased	off	1
0	1	forward biased	reverse biased	off	1
1	0	reverse biased	forward biased	off	1
1	1	reverse biased	reverse biased	on	0

we can also implement other types of logic circuits using the diode-transistor logic family.

advantages of dtl family

the following are some key advantages of diode-transistor logic family −

dtl circuits are easy and simple to design and implement, as they consist of only diodes, transistors, and resistors.
dtl circuits are cost-effective as they use basic electronic components like diodes and transistors which are generally cheap.
dtl circuits have good noise immunity. hence, these circuits are relatively less susceptible to noise and interference than some other types of logic families.
dtl circuits have high fan-out. the power dissipation in dtl circuits is comparatively low.

limitations of dtl family

apart from the advantages given above, the dtl circuits also have some disadvantages which are listed below −

dtl family circuits require higher amount of power as compared to other logic families.
dtl circuits consist of a greater number of elements than other types of logic families.
dtl circuits have a moderate speed of operation. this is due to high propagation delay.
dtl circuits are not suitable to design more complex digital circuits due to increased complexity and size of the circuit.

applications of dtl family

the following are some common applications of diode-transistor logic family −

dtl family was popular in early digital computers and other digital systems.
these days, dtl circuits are mainly used for educational purposes to explain the implementation of digital logic designs to students.
dtl circuits are used to design custom electronic projects.

transistor-transistor logic (ttl)

transistor-transistor logic (ttl) is one of the most popular logic family in the field of digital electronics. in this logic family, the transistor is the key functional element which is operated as a switch to perform the logical operations.

let us now understand how we can design a logic circuit in ttl family. the following figure shows a two-input nand gate −

here, a and b are the input terminals and y is the output terminal. the operation of this circuit is summarized in the following table.

input a	input b	emitter junction of transistor t₁	emitter junction of transistor t₂	transistor t₂ and t₃	output y
0	0	forward biased	forward biased	off	1
0	1	forward biased	reverse biased	off	1
1	0	reverse biased	forward biased	off	1
1	1	reverse biased	reverse biased	on	0

in the same manner, we can also design other logic gates in the transistor-transistor logic (ttl) family.

advantages of ttl family

here are some of the key advantages of ttl family −

ttl circuits have high speeds of operation and hence well-suited to use in high-speed digital systems.
ttl circuits are standardized to make them compatible with a variety of digital circuits and systems.
ttl circuits have good noise immunity. thus, they are suitable to use in noisy environments.

disadvantages of ttl family

although, ttl circuits have several advantages as listed above. but they also have some disadvantages which are given below −

ttl circuits consume more power than other types of logic families. this limitation makes the ttl circuits less energy efficient.
ttl circuits generate significant heat during operation and this is due to high power consumption. thus, a proper heat management system is required.
ttl logic levels are relatively strict, requiring specific voltage levels for proper operation. this can sometimes lead to compatibility issues with other logic families.
ttl circuits have a significant propagation delay that limit their use in certain high-speed systems.

applications of ttl family

transistor-transistor logic (ttl) family are widely used in various applications in the field of digital electronics. some of the common applications of ttl family are listed below −

ttl circuits are widely used in digital computers, memory units, cpus, etc.
ttl circuits are also used in embedded systems for different purposes such as interfacing with sensors, processing data in real-time applications, and more.
in communication systems, ttl circuits are for signal conditioning, protocol handling, data processing, etc. ttl circuits are commonly used in a variety of testing and measuring instruments.

conclusion

in conclusion, a logic family is a set of digital circuits that share same technical parameters such as logic levels, voltage levels, processing speed, etc. in this chapter, we explained the most commonly used digital logic families viz. rtl, dtl, and ttl, along with their advantages, disadvantages, and applications.

microprocessing unit is synonymous to central processing unit, cpu used in traditional computer. microprocessor (mpu) acts as a device or a group of devices which do the following tasks.

communicate with peripherals devices
provide timing signal
direct data flow
perform computer tasks as specified by the instructions in memory

8085 microprocessor

the 8085 microprocessor is an 8-bit general purpose microprocessor which is capable to address 64k of memory. this processor has forty pins, requires +5 v single power supply and a 3-mhz single-phase clock.

block diagram

alu

the alu perform the computing function of microprocessor. it includes the accumulator, temporary register, arithmetic & logic circuit & and five flags. result is stored in accumulator & flags.

block diagram

accumulator

it is an 8-bit register that is part of alu. this register is used to store 8-bit data & in performing arithmetic & logic operation. the result of operation is stored in accumulator.

diagram

flags

flags are programmable. they can be used to store and transfer the data from the registers by using instruction. the alu includes five flip-flops that are set and reset according to data condition in accumulator and other registers.

s (sign) flag − after the execution of an arithmetic operation, if bit d₇ of the result is 1, the sign flag is set. it is used to signed number. in a given byte, if d₇ is 1 means negative number. if it is zero means it is a positive number.
z (zero) flag − the zero flag is set if alu operation result is 0.
ac (auxiliary carry) flag − in arithmetic operation, when carry is generated by digit d3 and passed on to digit d₄, the ac flag is set. this flag is used only internally bcd operation.
p (parity) flag − after arithmetic or logic operation, if result has even number of 1s, the flag is set. if it has odd number of 1s, flag is reset.
c (carry) flag − if arithmetic operation result is in a carry, the carry flag is set, otherwise it is reset.

register section

it is basically a storage device and transfers data from registers by using instructions.

stack pointer (sp) − the stack pointer is also a 16-bit register which is used as a memory pointer. it points to a memory location in read/write memory known as stack. in between execution of program, sometime data to be stored in stack. the beginning of the stack is defined by loading a 16-bit address in the stack pointer.
program counter (pc) − this 16-bit register deals with fourth operation to sequence the execution of instruction. this register is also a memory pointer. memory location have 16-bit address. it is used to store the execution address. the function of the program counter is to point to memory address from which next byte is to be fetched.
storage registers − these registers store 8-bit data during a program execution. these registers are identified as b, c, d, e, h, l. they can be combined as register pair bc, de and hl to perform some 16 bit operations.

time and control section

this unit is responsible to synchronize microprocessor operation as per the clock pulse and to generate the control signals which are necessary for smooth communication between microprocessor and peripherals devices. the rd bar and wr bar signals are synchronous pulses which indicates whether data is available on the data bus or not. the control unit is responsible to control the flow of data between microprocessor, memory and peripheral devices.

pin diagram

all the signal can be classified into six groups

sr.no	group	description
1	address bus	the 8085 microprocessor has 8 signal line, a₁₅ - a₈ which are uni directional and used as a high order address bus.
2	data bus	the signal line ad7 - ad0 are bi-directional for dual purpose. they are used as low order address bus as well as data bus.
3	control signal and status signal	control signal rd bar − it is a read control signal (active low). if it is active then memory read the data. wr bar − it is write control signal (active low). it is active when written into selected memory. status signal ale (address latch enable) − when ale is high. 8085 microprocessor use address bus. when ale is low. 8085 microprocessor is use data bus. io/m bar − this is a status signal used to differentiate between i/o and memory operations. when it is high, it indicate an i/o operation and when it is low, it indicate memory operation. s₁ and s₀ − these status signals, similar to i/o and memory bar, can identify various operations, but they are rarely used in small system.
4	power supply and frequency signal	v_cc − +5v power supply. v_ss − ground reference. x, x − a crystal is connected at these two pins. the frequency is internally divided by two operate system at 3-mhz, the crystal should have a frequency of 6-mhz. clk out − this signal can be used as the system clock for other devices.
5	externally initiated signal	intr (i/p) − interrupt request. inta bar (o/p) − it is used as acknowledge interrupt. trap (i/p) − this is non maskable interrupt and has highest priority. hold (i/p) − it is used to hold the executing program. hlda (o/p) − hold acknowledge. ready (i/p) − this signal is used to delay the microprocessor read or write cycle until a slow responding peripheral is ready to accept or send data. reset in bar − when the signal on this pin goes low, the program counter is set to zero, the bus are tri-stated, & mpu is reset. reset out − this signal indicate that mpu is being reset. the signal can be used to reset other devices. rst 7.5, rst 6.5, rst 5.5 (request interrupt) − it is used to transfer the program control to specific memory location. they have higher priority than intr interrupt.
6	serial i/o ports	the 8085 microprocessor has two signals to implement the serial transmission serial input data and serial output data.

instruction format

each instruction is represented by a sequence of bits within the computer. the instruction is divided into group of bits called field. the way instruction is expressed is known as instruction format. it is usually represented in the form of rectangular box. the instruction format may be of the following types.

variable instruction formats

these are the instruction formats in which the instruction length varies on the basis of opcode & address specifiers. for example, vax instruction vary between 1 and 53 bytes while x86 instruction vary between 1 and 17 bytes.

format

advantage

these formats have good code density.

drawback

these instruction formats are very difficult to decode and pipeline.

fixed instruction formats

in this type of instruction format, all instructions are of same size. for example, mips, power pc, alpha, arm.

format

advantage

they are easy to decode & pipeline.

drawback

they don't have good code density.

hybrid instruction formats

in this type of instruction formats, we have multiple format length specified by opcode. for example, ibm 360/70, mips 16, thumb.

format

advantage

these compromise between code density & instruction of these type are very easy to decode.

addressing modes

addressing mode provides different ways for accessing an address to given data to a processor. operated data is stored in the memory location, each instruction required certain data on which it has to operate. there are various techniques to specify address of data. these techniques are called addressing modes.

direct addressing mode − in the direct addressing mode, address of the operand is given in the instruction and data is available in the memory location which is provided in instruction. we will move this data in desired location.
indirect addressing mode − in the indirect addressing mode, the instruction specifies a register which contain the address of the operand. both internal ram and external ram can be accessed via indirect addressing mode.
immediate addressing mode − in the immediate addressing mode, direct data is given in the operand which move the data in accumulator. it is very fast.
relative addressing mode − in the relative address mode, the effective address is determined by the index mode by using the program counter in stead of general purpose processor register. this mode is called relative address mode.
index addressing mode − in the index address mode, the effective address of the operand is generated by adding a content value to the contents of the register. this mode is called index address mode.

4-bit code				even parity
a	b	c	d	p
0	0	0	0	0
0	0	0	1	1
0	0	1	0	1
0	0	1	1	0
0	1	0	0	1
0	1	0	1	0
0	1	1	0	0
0	1	1	1	1
1	0	0	0	1
1	0	0	1	0
1	0	1	0	0
1	0	1	1	1
1	1	0	0	0
1	1	0	1	1
1	1	1	0	1
1	1	1	1	0

4-bit code				odd parity
a	b	c	d	p
0	0	0	0	1
0	0	0	1	0
0	0	1	0	0
0	0	1	1	1
0	1	0	0	0
0	1	0	1	1
0	1	1	0	1
0	1	1	1	0
1	0	0	0	0
1	0	0	1	1
1	0	1	0	1
1	0	1	1	0
1	1	0	0	1
1	1	0	1	0
1	1	1	0	0
1	1	1	1	1

4-bit code				even parity
a	b	c	d	p
0	0	0	0	0
0	0	0	1	1
0	0	1	0	1
0	0	1	1	0
0	1	0	0	1
0	1	0	1	0
0	1	1	0	0
0	1	1	1	1
1	0	0	0	1
1	0	0	1	0
1	0	1	0	0
1	0	1	1	1
1	1	0	0	0
1	1	0	1	1
1	1	1	0	1
1	1	1	1	0

4-bit code				odd parity
a	b	c	d	p
0	0	0	0	1
0	0	0	1	0
0	0	1	0	0
0	0	1	1	1
0	1	0	0	0
0	1	0	1	1
0	1	1	0	1
0	1	1	1	0
1	0	0	0	0
1	0	0	1	1
1	0	1	0	1
1	0	1	1	0
1	1	0	0	1
1	1	0	1	0
1	1	1	0	0
1	1	1	1	1

4-bit code				even parity
a	b	c	d	p
0	0	0	0	0
0	0	0	1	1
0	0	1	0	1
0	0	1	1	0
0	1	0	0	1
0	1	0	1	0
0	1	1	0	0
0	1	1	1	1
1	0	0	0	1
1	0	0	1	0
1	0	1	0	0
1	0	1	1	1
1	1	0	0	0
1	1	0	1	1
1	1	1	0	1
1	1	1	1	0

4-bit code				odd parity
a	b	c	d	p
0	0	0	0	1
0	0	0	1	0
0	0	1	0	0
0	0	1	1	1
0	1	0	0	0
0	1	0	1	1
0	1	1	0	1
0	1	1	1	0
1	0	0	0	0
1	0	0	1	1
1	0	1	0	1
1	0	1	1	0
1	1	0	0	1
1	1	0	1	0
1	1	1	0	0
1	1	1	1	1

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